PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURES
A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.
1 . (canceled)
2 . A method, comprising:
placing a coupling mechanism material layer on a backside of a wafer that has devices fabricated on a frontside thereof;
placing a one-piece panel of spacer blocks on the coupling mechanism material layer on the backside of the wafer;
activating the coupling mechanism material layer to bond the spacer blocks in the one-piece panel of spacer blocks to the backside of the wafer; and
singulating the wafer to separate individual vertical device stacks, each of the individual vertical device stacks including a device die bonded to a spacer block.
3 . The method of claim 2 , wherein each spacer block in the one-piece panel of spacer blocks is connected to adjacent spacer blocks by connecting strips, and wherein the connecting strips mechanically hold together the spacer blocks in the one-piece panel of spacer blocks as a single piece or unit.
4 . The method of claim 2 , each spacer block is made of a metal or a metal alloy.
5 . The method of claim 4 , wherein the metal or the metal alloy includes at least one of copper (Cu), aluminum (Al), copper-molybdenum (CuMo), aluminum silicon carbide composite (AlSiC), or aluminum silicon magnesium alloy (AlSiMg).
6 . The method of claim 4 , wherein a side of each spacer block facing the coupling mechanism material layer is coated with a plated silver layer.
7 . The method of claim 3 , wherein singulating the wafer to separate the individual vertical device stacks includes cutting the connecting strips that mechanically hold together the spacer blocks in the one-piece panel of spacer blocks.
8 . The method of claim 2 further comprising depositing a passivation layer on exposed sides of the individual vertical device stacks in a wafer-level deposition process.
9 . The method of claim 2 , wherein activating the coupling mechanism material layer to bond the spacer blocks to the backside of the wafer includes at least one of pressure sintering, solder reflow and fusion bonding.
10 . The method of claim 2 , wherein the device die includes at least one of a fast recovery diode (FRD) or an insulated gate bipolar transistor (IGBT).
11 . The method of claim 2 , further comprising thinning the wafer prior to placing the coupling mechanism material layer and placing the one-piece panel of spacer blocks on the coupling mechanism material layer on the backside of the wafer.
12 . The method of claim 11 , wherein thinning the wafer includes back grinding an inner portion of the wafer while leaving a wafer support ring at an edge of the wafer.
13 . The method of claim 2 , wherein the device die is about 100 microns thick or less.
14 . The method of claim 2 , wherein the device die includes a power device having a size that is greater than 25 square millimeters.
15 . The method of claim 2 , wherein the spacer block has thickness in a range of about 100 microns to 2500 microns, and wherein the coupling mechanism material layer has thickness in a range of about 50 microns to 300 microns.
16 . An assembly, comprising:
a semiconductor wafer with an array of devices fabricated on a frontside thereof;
a coupling mechanism material layer disposed on a backside of the semiconductor wafer; and
a one-piece panel of spacer blocks disposed on the coupling mechanism material layer, the one-piece panel of spacer blocks including an array of spacer blocks with connecting strips of metal joining adjacent spacer blocks, the spacer blocks in the one-piece panel of spacer blocks being bonded to the backside of the semiconductor wafer,
the connecting strips joining adjacent spacer blocks in the one-piece panel of spacer blocks being severable in a wafer singulation action to separate individual vertical device stacks, each of the individual vertical device stacks including a device die bonded to a spacer block.
17 . The assembly of claim 16 , wherein the spacer blocks are made of a metal or a conductive metal alloy including at least one of copper (Cu), aluminum (Al), copper-molybdenum (CuMo), aluminum silicon carbide composite (AlSiC), or aluminum silicon magnesium alloy (AlSiMg).
18 . The assembly of claim 16 , wherein the device die is about 100 microns thick or less.
19 . The assembly of claim 16 , wherein the coupling mechanism material layer disposed on the backside of the semiconductor wafer has a thickness greater than about 200 microns.
20 . The assembly of claim 16 , wherein the one-piece panel of spacer blocks has a planar shape conforming to a shape of the semiconductor wafer.
21 . The assembly of claim 16 , wherein each of the individual vertical device stacks is configured to be moved and placed in a circuit package as a single pre-formed unit.