Gate drivers for stacked transistor amplifiers
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
1. A method for biasing a transistor stack for operation according to at least a first mode and a second mode, the method comprising:
during the first mode of operation, providing biasing voltages to gates of the transistors of the stack, except an input transistor, via high impedance nodes of a first resistive ladder network; and
during the second mode of operation, providing biasing voltages to said gates via low impedance nodes of a second resistive ladder network and wherein a current through the second resistive ladder network during the second mode of operation is substantially larger than a current through the first resistive ladder network during the first mode of operation.
2. The method according to claim 1 , wherein:
the first mode of operation is a standby mode for no amplification through the transistor stack, and
the second mode of operation is an active mode for amplification through the transistor stack.
3. The method according to claim 1 , wherein:
in the first mode of operation, a current conducted through the transistor stack is a leakage current; and
in the second mode of operation, a current conducted through the transistor stack provides an amplification of an RF signal input to the transistor stack.
4. The method according to claim 1 , wherein:
high resistance values of the first resistive ladder network provide the high impedance nodes, and
low resistance values of the second resistive ladder network provide the low impedance nodes, the low resistance values being substantially smaller than the high resistance values.
5. The method according to claim 1 , wherein:
the first mode of operation is a standby mode, and
the current through the first resistive ladder network during the first mode of operation is equal to, or less than, 3 μA.
6. The method according to claim 1 , wherein:
the second mode of operation is an active mode, and
the current through the second resistive ladder network during the second mode of operation is as large as 0.8 mA.
7. The method according to claim 1 , further comprising:
based on the providing,
coupling during the first mode of operation a respective first biasing voltage to each of said gates; and
coupling during the second mode of operation a respective second biasing voltage to each of said gates that is substantially equal to the respective first biasing voltage.
8. The method according to claim 1 , further comprising:
based on the providing,
coupling during the first mode of operation a respective first biasing voltage to each of said gates; and
coupling during the second mode of operation a respective second biasing voltage to each of said gates,
wherein for at least one gate of said gates, the respective first biasing voltage is different from the respective second biasing voltage.
9. The method according to claim 1 , wherein:
the transistor stack comprises one or more gate capacitors each connected between a gate of a transistor of the transistor stack, except an input transistor of the transistor stack, and a reference voltage.
10. A circuital arrangement comprising:
a transistor stack configured to operate as an amplifier, the transistor stack comprising an input transistor and one or more cascode transistors; and
a biasing circuit coupled to one or more gates of the one or more cascode transistors, the biasing circuit comprising:
a first resistive ladder network comprising one or more high impedance nodes; and
a second resistive ladder network comprising one or more low impedance nodes; wherein
during a first mode of operation of the circuital arrangement, the one or more high impedance nodes are coupled to the one or more gates to provide respective biasing voltages, and
during the second mode of operation, the one or more low impedance nodes are coupled to the one or more gates to provide respective biasing voltages and wherein a current through the second resistive ladder network during the second mode of operation is substantially larger than a current through the first resistive ladder network during the first mode of operation.
11. The circuital arrangement according to claim 10 , wherein:
a ratio of a current through the second resistive ladder network during the second mode of operation to a current through the first resistive ladder network during the first mode of operation is equal to, or larger than, 100.
12. The circuital arrangement according to claim 10 , wherein:
the first mode of operation is a standby mode for no amplification through the transistor stack, and
the second mode of operation is an active mode for amplification through the transistor stack.
13. The circuital arrangement according to claim 10 , wherein:
a current conducted through the transistor stack during the first mode of operation is a leakage current; and
a current conducted through the transistor stack during the second mode of operation provides an amplification of an RF signal provided to the input transistor.
14. The circuital arrangement according to claim 10 , wherein:
the first resistive ladder network comprises resistors with high resistance values that provide the high impedance nodes, and
the second resistive ladder network comprises resistors with low resistance values that provide the low impedance nodes, the low resistance values being substantially smaller than the high resistance values.
15. The circuital arrangement according to claim 10 , wherein:
for each of the one or more gates, the respective biasing voltage provided during the first mode of operation is substantially equal to the respective biasing voltage provided during the second mode of operation.
16. The circuital arrangement according to claim 10 , wherein:
for at least one of the one or more gates, the respective biasing voltage provided during the first mode of operation is different from the respective biasing voltage provided during the second mode of operation.
17. The circuital arrangement according to claim 10 , wherein the one or more low impedance nodes are coupled to the one or more gates via respective one or more switches.
18. The circuital arrangement according to claim 10 , wherein the one or more high impedance nodes are coupled to the one or more gates via respective one or more switches.