Semiconductor devices and semiconductor systems related to synchronization between clocks
A semiconductor device includes a command pulse generation circuit configured to generate a first command pulse in synchronization with a frequency division clock and to generate a second command pulse in synchronization with an inverted frequency division clock, based on a test write command. The semiconductor device also includes an alignment data generation circuit configured to align first internal data in an in-phase manner to generate first alignment data, based on the first command pulse, and to align second internal data in an out-of-phase manner to generate second alignment data, based on the second command pulse. The semiconductor device further includes a phase detection circuit configured to determine synchronization states of a clock and the frequency division clock, based on the first alignment data and the second alignment data.
1. A semiconductor device comprising:
a command pulse generation circuit configured to generate a first command pulse in synchronization with a frequency division clock and to generate a second command pulse in synchronization with an inverted frequency division clock, based on a test write command;
an alignment data generation circuit configured to align first internal data in an in-phase manner to generate first alignment data, based on the first command pulse, and to align second internal data in an out-of-phase manner to generate second alignment data, based on the second command pulse; and
a phase detection circuit configured to determine synchronization states of a clock and the frequency division clock, based on the first alignment data and the second alignment data.
2. The semiconductor device of claim 1 , further comprising a command decoder configured to sequentially generate a clock synchronization command and the test write command to perform a test write operation.
3. The semiconductor device of claim 1 , further comprising a frequency division clock generation circuit configured to divide a frequency of the clock to generate the frequency division clock and the inverted frequency division clock.
4. The semiconductor device of claim 1 , further comprising a data buffer configured to buffer first data generated to be the same as a data pattern to generate the first internal data, and to buffer second data generated to be the same as the data pattern to generate the second internal data.
5. The semiconductor device of claim 1 , wherein the command pulse generation circuit includes:
a first command pulse generation circuit configured to generate the first command pulse in synchronization with the frequency division clock when the test write command is generated; and
a second command pulse generation circuit configured to generate the second command pulse in synchronization with the inverted frequency division clock when the test write command is generated.
6. The semiconductor device of claim 1 , wherein the alignment data generation circuit includes:
a first alignment data generation circuit configured to align the first internal data in an in-phase manner to generate the first alignment data when the first command pulse is generated; and
a second alignment data generation circuit configured to align the second internal data in an out-of-phase manner to generate the second alignment data when the second command pulse is generated.
7. The semiconductor device of claim 1 , wherein the phase detection circuit is configured to determine that the clock and the frequency division clock are synchronized in an in-phase manner when the first alignment data is set to be in-phase with a data pattern and the second alignment data is not set to be out-of-phase with the data pattern.
8. The semiconductor device of claim 1 , wherein the phase detection circuit is configured to determine that the clock and the frequency division clock are synchronized in an out-of-phase manner when the first alignment data is not set to be in-phase with a data pattern and the second alignment data is set to be out-of-phase with the data pattern.
9. The semiconductor device of claim 1 , wherein the phase detection circuit is configured to determine that the clock and the frequency division clock fail in synchronization when the first alignment data is set to be in-phase with a data pattern and the second alignment data is set to be out-of-phase with the data pattern.
10. The semiconductor device of claim 1 , wherein the phase detection circuit is configured to determine that the clock and the frequency division clock fail in synchronization when the first alignment data is not set to be in-phase with a data pattern and the second alignment data is not set to be out-of-phase with the data pattern.
11. A semiconductor device comprising:
a command pulse generation circuit configured to generate a first command pulse in synchronization with a frequency division clock, and to generate a second command pulse in synchronization with an inverted frequency division clock, based on a test write command;
an alignment data generation circuit configured to align internal data in an in-phase manner to generate first alignment data, based on the first command pulse, and to align the internal data in an out-of-phase manner to generate second alignment data, based on the second command pulse; and
a phase detection circuit configured to determine synchronization states of a clock and the frequency division clock, based on the first alignment data and the second alignment data.
12. The semiconductor device of claim 11 , further comprising a data buffer configured to buffer data generated to be the same as a data pattern to generate the internal data.
13. The semiconductor device of claim 11 , wherein the alignment data generation circuit includes:
a first alignment data generation circuit configured to align the internal data in an in-phase manner to generate the first alignment data when the first command pulse is generated; and
a second alignment data generation circuit configured to align the internal data in an out-of-phase manner to generate the second alignment data when the second command pulse is generated.
14. A semiconductor device comprising:
a selection clock generation circuit configured to generate a selection clock from a frequency division clock, based on a phase selection signal;
a command pulse generation circuit configured to generate a command pulse in synchronization with the selection clock, based on a test write command;
an alignment data generation circuit configured to align internal data to generate alignment data, based on the command pulse; and
a phase detection circuit configured to determine synchronization states of a clock and the frequency division clock, based on the phase selection signal and the alignment data.
15. The semiconductor device of claim 14 ,
wherein the selection clock generation circuit is configured to receive the phase selection signal, and
wherein the phase selection signal is set to have a first logic level to generate the alignment data aligned in an in-phase manner in a test write operation, and is set to have a second logic level to generate the alignment data aligned in an out-of-phase manner in the test write operation.
16. The semiconductor device of claim 14 , wherein the selection clock generation circuit is configured to output the frequency division clock as the selection clock, based on the phase selection signal in a test write operation, and to invert the frequency division clock to output an inverted frequency division clock as the selection clock, based on the phase selection signal in the test write operation.
17. The semiconductor device of claim 14 , wherein the command pulse generation circuit is configured to:
generate the command pulse in synchronization with the selection clock when the frequency division clock is output as the selection clock, and
generate the command pulse in synchronization with the selection clock when the frequency division clock is inverted to be output as the selection clock, when the test write command is generated for the test write operation.
18. The semiconductor device of claim 14 , wherein the alignment data generation circuit is configured to:
align the internal data in an in-phase manner to generate the alignment data, based on the command pulse when the command pulse is generated in synchronization with the selection clock generated from the frequency division clock; and
align the internal data in an out-of-phase manner to generate the alignment data, based on the command pulse when the command pulse is generated in synchronization with the selection clock generated by inverting the frequency division clock.
19. A semiconductor system comprising:
a controller configured to apply a command, a clock, a data clock, first data, and second data; and
a semiconductor device configured to sequentially generate a clock synchronization command and a test write command, based on the command for performing a test write operation, to divide a frequency of the data clock to generate a frequency division clock and an inverted frequency division clock, to align first internal data and second internal data generated by buffering the first data and the second data to generate first alignment data and second align data, based on a first command pulse and a second command pulse generated in synchronization with the frequency division clock and the inverted frequency division clock, and to determine synchronization states of the clock and the frequency division clock, based on the first alignment data and the second align data.
20. A semiconductor system comprising:
a controller configured to apply a command, a clock, a data clock, and data; and
a semiconductor device configured to sequentially generate a clock synchronization command and a test write command, based on the command for performing a test write operation, to divide a frequency of the data clock to generate a frequency division clock and an inverted frequency division clock, to align internal data generated by buffering the data to generate first alignment data and second align data, based on a first command pulse and a second command pulse generated in synchronization with the frequency division clock and the inverted frequency division clock, and to determine synchronization states of the clock and the frequency division clock, based on the first alignment data and the second alignment data.
21. A semiconductor system comprising:
a controller configured to apply a command, a clock, a data clock, and data; and
a semiconductor device configured to sequentially generate a clock synchronization command and a test write command, based on the command for performing a test write operation, to divide a frequency of the data clock to generate a frequency division clock, to output the frequency division clock or an inverted frequency division clock as a selection clock, based on a phase selection signal, to align internal data generated by buffering the data to generate alignment data, based on a command pulse generated in synchronization with the selection clock, and to determine synchronization states of the clock and the frequency division clock, based on the phase selection signal and the alignment data.