Method and system for in-line ECC protection
A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.
1. A device comprising:
a memory configured to store data according to an address space; and
a circuit coupled to the memory and configured to:
receive a first write command associated with a first set of data;
generate a first set of error correction code (ECC) data for the first set of data;
receive a second write command associated with a second set of data;
generate second set of ECC data for the second set of data;
cause the first set of data to be stored in the memory;
cause the second set of data to be stored, in the memory, adjacent to the first set of data in the address space;
cause the first set of ECC data to be stored, in the memory, adjacent to and prior to the first set of data in the address space; and
cause the second set of ECC data to be stored, in the memory, adjacent to and after the second set of data in the address space.
2. The device of claim 1 , wherein the circuit is configured to:
receive a third write command associated with a third set of data;
generate third set of ECC data for the third set of data;
cause the third set of ECC data to be stored, in the memory, adjacent to the second set of ECC data in the address space; and
cause the third set of data to be stored, in the memory, adjacent to and after the third set of ECC data in the address space.
3. The device of claim 1 , wherein:
the first write command is a read-modify-write command that specifies a third set of data; and
the circuit includes a read-modify-write circuit configured to, based on the read-modify-write command:
read a fourth set of data from the memory; and
merge the third set of data with the fourth set of data to produce the first set of data.
4. The device of claim 1 , wherein the memory is a random-access memory.
5. The device of claim 1 , wherein the first set of ECC data is Single-Error-Correct-Double-Error-Detect (SECDED) data.
6. The device of claim 1 , wherein the first set of ECC data encodes at least one of: an address of the first set of data or an address of the first set of ECC data.
7. The device of claim 1 , wherein:
the first set of data has a size of 512 bytes; and
the first set of ECC data has a size of 512 bytes.
8. A device comprising:
a memory configured to store data according to an address space;
a processor configured to provide a first write command to write a first set of data and a second write command to write a second set of data; and
a memory control circuit coupled between the memory and the processor and configured to:
receive the first write command and the second write command; and
cause the first set of data, a first set of error correction code (ECC) data associated with the first set of data, the second set of data, and a second set of ECC data associated with the second set of data to be stored in the memory such that:
the first set of data is adjacent to the second set of data in the address space;
the first set of ECC data is adjacent to and prior to the first set of data in the address space; and
the second set of ECC data is adjacent to and after the second set of data in the address space.
9. The device of claim 8 , wherein the memory control circuit includes an ECC calculation circuit configured to generate the first set of ECC data and the second set of ECC data.
10. The device of claim 8 , wherein:
the processor is configured to provide a third write command to write a third set of data; and
the memory control circuit is configured to cause the third set of data and a third set of ECC data associated with the third set of data to be stored in the memory such that:
the third set of ECC data is adjacent to the second set of ECC data in the address space; and
the third set of data is adjacent to and after the third set of ECC data in the address space.
11. The device of claim 8 , wherein the memory is a random-access memory.
12. The device of claim 8 , wherein the first set of ECC data is Single-Error-Correct-Double-Error-Detect (SECDED) data.
13. The device of claim 8 , wherein the first set of ECC data encodes at least one of: an address of the first set of data or an address of the first set of ECC data.
14. The device of claim 8 , wherein:
the first set of data has a size of 512 bytes; and
the first set of ECC data has a size of 512 bytes.
15. A method comprising:
receiving a first set of data;
generating a first set of error correction code (ECC) data based on the first set of data;
receiving a second set of data;
generating a second set of ECC data based on the second set of data;
storing the first set of data, the first set of ECC data, the second set of data, and a second set of ECC data in a memory such that:
the first set of data is adjacent to the second set of data in an address space;
the first set of ECC data is adjacent to and prior to the first set of data in the address space; and
the second set of ECC data is adjacent to and after the second set of data in the address space.
16. The method of claim 15 , wherein the receiving of the first set of data include:
receiving a read-modify-write command that specifies a third set of data; and
based on the read-modify-write command:
reading a fourth set of data from the memory; and
merging the third set of data with the fourth set of data to produce the first set of data.
17. The method of claim 15 , wherein the memory is a random-access memory.
18. The method of claim 15 , wherein the first set of ECC data is Single-Error-Correct-Double-Error-Detect (SECDED) data.
19. The method of claim 15 , wherein the first set of ECC data encodes at least one of: an address of the first set of data or an address of the first set of ECC data.
20. The method of claim 15 , wherein:
the first set of data has a size of 512 bytes; and
the first set of ECC data has a size of 64 bytes.