Geometry kick distribution in graphics processor
Disclosed techniques relate to parsing and assigning sets of geometry work to distributed hardware slots. In some embodiments, graphics control circuitry implements a plurality of logical slots. Control circuitry may assign a parse version of a set of geometry work to distributed hardware slots of one or more of the graphics processor sub-units that each implement multiple distributed hardware slots. Control circuitry may determine a number of segments for the set of geometry work based on execution of the parse version and assign determined segments to distributed hardware slots of respective graphics processor sub-units for execution. Stitch circuitry may stitch results of the segments processed by the assigned distributed hardware slots.
1 . An apparatus, comprising:
a set of graphics processor sub-units that each implement multiple distributed hardware slots; and
control circuitry configured to:
assign a parse version of a set of geometry work to one or more distributed hardware slots of one or more of the graphics processor sub-units;
determine a number of segments for the set of geometry work based on execution of the parse version; and
assign an execution version of determined segments of the set of geometry work to distributed hardware slots of respective graphics processor sub-units for execution; and
stitch circuitry configured to stitch results of the execution version of the segments of the set of geometry work executed by the assigned one or more distributed hardware slots.
2 . The apparatus of claim 1 , wherein the stitch circuitry includes:
stitch control circuitry configured to:
assign stitch work for one or more first data structure categories to hardware stitch slots in primary control circuitry; and
assign stitch work for one or more second data structure categories to distributed hardware stitch slots in respective graphics processor sub-units, wherein the distributed hardware stitch slots include respective memory interfaces to access a memory that stores data structures to be stitched.
3 . The apparatus of claim 2 , wherein the one or more first data structure categories utilize less memory space than the one or more second data structure categories.
4 . The apparatus of claim 2 , wherein:
one or more first data structure categories include a layer identifier cache and a list of closed pages; and
one or more second data structure categories include tile region array headers.
5 . The apparatus of claim 1 , wherein the control circuitry is configured to:
assign parse work for the set of geometry work to at most one distributed hardware slot of a given graphics processor sub-unit; and
assign segment execution work to at most one distributed hardware slot of a given graphics processor sub-unit.
6 . The apparatus of claim 1 , wherein the control circuitry is configured to:
assign the parse version to all graphics processor sub-units in a set of graphics processor sub-units; and
serially assign segments of the determined number of segments to available graphics processor sub-units in the set.
7 . The apparatus of claim 1 , wherein the stitch circuitry is configured to stitch results on multiple graphics processor sub-units that were assigned a segment for the set of geometry work.
8 . The apparatus of claim 1 , wherein the control circuitry is configured to allow different sets of geometry work to execute in parallel on different distributed hardware slots only if the different sets of geometry work share a parameter buffer.
9 . The apparatus of claim 1 , wherein the control circuitry is configured to dynamically change the number of distributed hardware slots assigned to the set of geometry work during execution of the set of geometry work.
10 . The apparatus of claim 1 , wherein one or more graphics processor sub-units of the set are configured to execute fragment work that operates on the stitched results.
11 . A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
a set of graphics processor sub-units that each implement multiple distributed hardware slots; and
control circuitry configured to:
assign a parse version of a set of geometry work to one or more distributed hardware slots of one or more of the graphics processor sub-units;
determine a number of segments for the set of geometry work based on execution of the parse version; and
assign an execution version of determined segments of the set of geometry work to distributed hardware slots of respective graphics processor sub-units for execution; and
stitch circuitry configured to stitch results of the execution version of the segments of the set of geometry work executed by the assigned one or more distributed hardware slots.
12 . The non-transitory computer readable storage of claim 11 , wherein the stitch circuitry includes:
stitch control circuitry configured to:
assign stitch work for one or more first data structure categories to hardware stitch slots in primary control circuitry; and
assign stitch work for one or more second data structure categories to distributed hardware stitch slots in respective graphics processor sub-units, wherein the distributed hardware stitch slots include respective memory interfaces to access a memory that stores data structures to be stitched.
13 . The non-transitory computer readable storage of claim 12 , wherein:
one or more first data structure categories include a layer identifier cache and a list of closed pages; and
one or more second data structure categories include tile region array headers.
14 . The non-transitory computer readable storage of claim 11 , wherein the control circuitry is configured to:
assign parse work for the set of geometry work to at most one distributed hardware slot of a given graphics processor sub-unit; and
assign segment execution work to at most one distributed hardware slot of a given graphics processor sub-unit.
15 . The non-transitory computer readable storage of claim 11 , wherein the control circuitry is configured to:
assign the parse version to all graphics processor sub-units in a set of graphics processor sub-units; and
serially assign segments of the determined number of segments to available graphics processor sub-units in the set.
16 . The non-transitory computer readable storage of claim 11 , wherein the control circuitry is configured to dynamically change the number of distributed hardware slots assigned to the set of geometry work during execution of the set of geometry work.
17 . A method, comprising:
assigning, by a computing device, a parse version of a set of geometry work to one or more distributed hardware slots of one or more graphics processor sub-units;
determining, by the computing device, a number of segments for the set of geometry work based on execution of the parse version;
assigning, by the computing device, an execution version of determined segments of the set of geometry work to distributed hardware slots of respective graphics processor sub-units for execution; and
stitching, by the computing device, results of the execution version of the segments of the set of geometry work executed by the assigned one or more distributed hardware slots.
18 . The method of claim 17 , further comprising:
assigning, by the computing device, work for one or more first data structure categories to hardware stitch slots in primary control circuitry; and
assigning, by the computing device, work for one or more second data structure categories to distributed hardware stitch slots in respective graphics processor sub-units, wherein the distributed hardware stitch slots include respective memory interfaces to access a memory that stores data structures to be stitched.
19 . The method of claim 18 , wherein:
one or more first data structure categories include a layer identifier cache and a list of closed pages; and
one or more second data structure categories include tile region array headers.
20 . The method of claim 18 , further comprising:
assigning, by the computing device, parse work for the set of geometry work to at most one distributed hardware slot of a given graphics processor sub-unit; and
assigning, by the computing device, segment execution work to at most one distributed hardware slot of a given graphics processor sub-unit.