Chiplet architecture for late bind SKU fungibility
Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.
1 . A non-transitory machine-readable medium storing instructions thereon, the instructions to cause one or more processors to perform operations comprising:
loading a functional specification for a modular parallel processor from a machine-readable storage medium, the functional specification including two or more of a functionality target, a power target, and a performance target;
determining a set of multiple chiplets for the modular parallel processor according to the functional specification of the modular parallel processor and a database of available chiplets that includes an inventory of tested and binned chiplets;
determining a base chiplet die configuration according to a set of aperture sizes associated with the set of multiple chiplets and aperture sizes respectively associated with chiplet slots of base dies of a plurality of base chiplet dies, wherein the plurality of base chiplet dies include multiple configurations of chiplet slots associated with different aperture sizes and the chiplet slots are respectively configured to couple with a chiplet having a corresponding aperture size; and
configuring the modular parallel processor for manufacturing using the base chiplet die configuration and the set of multiple chiplets, including generating an electronic manufacturing manifest that includes identifiers for one or more base chiplet dies of the base chiplet die configuration and chiplets of the set of multiple chiplets.
2 . The non-transitory machine-readable medium as in claim 1 , wherein the plurality of base chiplet die configurations includes a first base chiplet die configuration having a plurality of chiplet slots of uniform aperture sizes and a second based chiplet configuration having a plurality of chiplet slots of non-uniform aperture sizes.
3 . The non-transitory machine-readable medium as in claim 2 , wherein determining the set of multiple chiplets for the modular parallel processor according to the functional specification includes selecting chiplets that conform with the functionality target, power target, and/or performance target of the functional specification.
4 . The non-transitory machine-readable medium as in claim 1 , wherein the functional specification includes a number and type of functional units and an associated power or performance target and the database of available chiplets includes a number and type of functional units and a power or performance bin associated respectively with the available chiplets.
5 . The non-transitory machine-readable medium as in claim 4 , wherein to determine the set of multiple chiplets includes selecting chiplets that conform with the number and type of functional units and the associated power or performance target.
6 . The non-transitory machine-readable medium as in claim 4 , wherein selecting chiplets that conform with the number and type of functional units includes selecting chiplets that include one or more of a matrix accelerator and an integer logic unit or a floating point unit.
7 . The non-transitory machine-readable medium as in claim 1 , wherein determining the base chiplet die configuration includes selecting a set of one or more base chiplet dies that provides at least a number of chiplet slots sufficient to accept the set of multiple chiplets determined for the modular parallel processor according to the aperture sizes associated with the set of multiple chiplets.
8 . The non-transitory machine-readable medium as in claim 7 , wherein determining the base chiplet die configuration includes determining a number of base chiplet dies and an interconnect configuration for the base chiplet dies.
9 . The non-transitory machine-readable medium as in claim 8 , wherein the electronic manufacturing manifest includes identifiers for at least one chiplet associated respectively with two or more layers of the modular parallel processor.
10 . The non-transitory machine-readable medium as in claim 9 , further comprising manufacturing the modular parallel processor, wherein manufacturing the modular parallel processor includes mounting the set of multiple chiplets to chiplet slots of the base chiplet dies.
11 . A data processing system comprising:
a memory device configured to store instructions; and
one or more processors coupled with the memory device and configured to execute the instructions, wherein the instructions cause the one or more processors to perform operations to:
load a functional specification for a modular parallel processor from a machine-readable storage medium, the functional specification including two or more of a functionality target, a power target, and a performance target;
determine a set of multiple chiplets for the modular parallel processor according to the functional specification of the modular parallel processor and a database of available chiplets that includes an inventory of tested and binned chiplets;
determine a base chiplet die configuration according to a set of aperture sizes associated with the set of multiple chiplets and aperture sizes respectively associated with chiplet slots of base dies of a plurality of base chiplet dies, wherein the plurality of base chiplet dies include multiple configurations of chiplet slots associated with different aperture sizes and the chiplet slots are respectively configured to couple with a chiplet having a corresponding aperture size; and
configure the modular parallel processor for manufacturing using the base chiplet die configuration and the set of multiple chiplets, including to generate an electronic manufacturing manifest that includes identifiers for one or more base chiplet dies of the base chiplet die configuration and chiplets of the set of multiple chiplets.
12 . The data processing system as in claim 11 , wherein the plurality of base chiplet die configurations includes a first base chiplet die configuration having a plurality of chiplet slots of uniform aperture sizes and a second based chiplet configuration having a plurality of chiplet slots of non-uniform aperture sizes.
13 . The data processing system as in claim 12 , wherein to determine the set of multiple chiplets for the modular parallel processor according to the functional specification includes to select chiplets that conform with the functionality target, power target, and/or performance target of the functional specification.
14 . The data processing system as in claim 11 , wherein the functional specification includes a number and type of functional units and an associated power or performance target and the database of available chiplets includes a number and type of functional units and a power or performance bin associated respectively with the available chiplets.
15 . The data processing system as in claim 14 , wherein to determine the set of multiple chiplets includes selecting chiplets that conform with the number and type of functional units and the associated power or performance target.
16 . The data processing system as in claim 14 , wherein to select chiplets that conform with the number and type of functional units includes to select chiplets that include one or more of a matrix accelerator and an integer logic unit or a floating point unit.
17 . The data processing system as in claim 11 , wherein to determine the base chiplet die configuration includes to select a set of one or more base chiplet dies that provides at least a number of chiplet slots sufficient to accept the set of multiple chiplets determined for the modular parallel processor according to the aperture sizes associated with the set of multiple chiplets.
18 . The data processing system as in claim 17 , wherein to determine the base chiplet die configuration includes to determine a number of base chiplet dies and an interconnect configuration for the base chiplet dies.
19 . The data processing system as in claim 18 , wherein the electronic manufacturing manifest includes identifiers for at least one chiplet associated respectively with two or more layers of the modular parallel processor.
20 . The data processing system as in claim 19 , wherein the operations additionally include to manufacture the modular parallel processor, including to mount the set of multiple chiplets to chiplet slots of the base chiplet dies.