Power delivery for multi-chip-package using in-package voltage regulator

1. A semiconductor structure, comprising:

a first substrate including a first surface and a second surface opposite to the first surface;

a first die disposed over the second surface of the first substrate;

a second die disposed over the second surface of the first substrate and adjacent to the first die;

a plurality of first conductive bumps disposed between the first substrate and the first die and between the first substrate and the second die;

a second substrate disposed below the first surface of the first substrate;

a plurality of second conductive bumps disposed between the first substrate and the second substrate;

an in-package voltage regulator (PVR) chip disposed over the second substrate;

a molding material disposed over the first substrate and surrounding the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip; and

an integrated passive die (IPD) chip comprising a capacitive device disposed in one or more trenches in a semiconductor substrate of the IPD chip, the semiconductor substrate of the IPD chip being arranged between the first substrate and the second substrate and being laterally surrounded by the plurality of second conductive bumps.

2. The semiconductor structure of claim 1 , wherein the PVR chip is arranged laterally adjacent to the first substrate, and is connected to the second substrate through some of the plurality of second conductive bumps.

3. The semiconductor structure of claim 2 , wherein the molding material directly contacts sidewalls of the PVR chip and is disposed between and contacts nearest neighboring sidewalls of the PVR chip and the first substrate.

4. The semiconductor structure of claim 2 , further comprising:

a thermal insulating material (TIM) disposed over and contacting an upper surface of the first die, disposed over and contacting an upper surface of the second die, and disposed over and contacting an upper surface of the PVR chip.

5. The semiconductor structure of claim 1 , wherein the PVR chip is arranged between the first substrate and the second substrate, and is laterally surrounded by the plurality of second conductive bumps.

6. The semiconductor structure of claim 1 , further comprising:

a plurality of third conductive bumps disposed below the second substrate.

7. The semiconductor structure of claim 6 , wherein the PVR chip is arranged under the second substrate, and is laterally surrounded by the plurality of third conductive bumps.

8. The semiconductor structure of claim 1 , wherein the PVR chip is arranged over first substrate.

9. The semiconductor structure of claim 1 , wherein the first die includes a first HPC processor, the second die includes a second HPC processor, the PVR chip provides power to the first HPC processor and the second HPC processor through the first conductive bumps, the first substrate, and the second conductive bumps, and wherein the IPD chip is placed directly beneath the first HPC processor of the first die.

10. The semiconductor structure of claim 1 , wherein the first substrate is an interposer substrate devoid of active semiconductor devices, and wherein the interposer substrate includes a decoupling capacitor structure disposed in a series of trenches in a surface of the interposer substrate.

11. The semiconductor structure of claim 1 :

wherein the first substrate is a first interposer substrate devoid of active semiconductor devices; and

wherein the second substrate is a second interposer substrate devoid of active semiconductor devices.

12. A semiconductor structure, comprising:

a first substrate including a first surface and a second surface opposite to the first surface;

a first die disposed over the second surface of the first substrate;

a second die disposed over the second surface of the first substrate and adjacent to the first die;

a plurality of first conductive bumps disposed between the first substrate and the first die and between the first substrate and the second die;

a second substrate disposed below the first surface of the first substrate;

a plurality of second conductive bumps disposed between the first substrate and the second substrate; and

an in-package voltage regulator (PVR) chip, the PVR chip including an inductor disposed over a semiconductor substrate, and the PVR chip being arranged between the first substrate and the second substrate and being laterally surrounded by the plurality of second conductive bumps.

13. The semiconductor structure of claim 12 , further comprising:

a molding material disposed over the first substrate and surrounding the first die, surrounding the second die, surrounding the plurality of first conductive bumps, surrounding the plurality of second conductive bumps, and surrounding the PVR chip.

14. The semiconductor structure of claim 12 , further comprising:

a first underfill material disposed over the first substrate and surrounding the plurality of first conductive bumps; and

a second underfill material disposed over the second substrate and surrounding the plurality of second conductive bumps and the PVR chip.

15. A semiconductor structure, comprising:

a first substrate including a first surface and a second surface opposite to the first surface;

a first die disposed over the second surface of the first substrate;

a second die disposed over the second surface of the first substrate and adjacent to the first die;

a plurality of first conductive bumps disposed between the first substrate and the first die and between the first substrate and the second die;

a second substrate disposed below the first surface of the first substrate;

an in-package voltage regulator (PVR) chip comprising a buck-converter disposed over the second substrate, and laterally spaced apart from a sidewall of the first substrate;

a plurality of second conductive bumps disposed between the first substrate and the second substrate and between the PVR chip and the second substrate; and

a molding material disposed over the second substrate and surrounding the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

16. The semiconductor structure of claim 15 , further comprising:

an integrated passive device (IPD) comprising a capacitive device disposed in one or more trenches in a semiconductor substrate of the IPD, the semiconductor substrate of the IPD being arranged between the first substrate and the second substrate and being laterally surrounded by the plurality of second conductive bumps.

17. The semiconductor structure of claim 15 , wherein the first substrate is an interposer substrate devoid of active semiconductor devices, and wherein the interposer substrate includes a decoupling capacitor structure disposed in a series of trenches in a surface of the interposer substrate.

18. The semiconductor structure of claim 15 , wherein the PVR chip comprises an inductor, and there is no active circuitry in the PVR chip directly above or directly below the inductor, and there is no active circuitry in the second substrate directly above or directly below the inductor.

19. The semiconductor structure of claim 12 , further comprising decoupling capacitors disposed on the second substrate opposite the plurality of second conductive bumps, the decoupling capacitors coupled to the PVR chip.

20. The semiconductor structure of claim 1 , wherein the IPD chip is spaced from the second substrate by the molding material.