Memory device
A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
1 . A method of providing a write voltage to a memory device, the method comprising:
generating a temperature adjusted reference voltage based on a Proportional to Absolute Temperature (PTAT) current and a Zero Temperature Coefficient (ZTC) current;
detecting an instantaneous write voltage of a bit line of a memory device;
comparing the instantaneous write voltage with the temperature adjusted reference voltage; and
regulating the instantaneous write voltage of the bit line based on comparing the instantaneous write voltage with the temperature adjusted reference voltage.
2 . The method of claim 1 , wherein generating the temperature adjusted reference voltage based on the PTAT current and the ZTC current comprises:
generating the PTAT current;
generating the ZTC current; and
generating the temperature adjusted reference voltage based on the PTAT current and the ZTC current.
3 . The method of claim 2 , wherein the PTAT current is proportional to temperature and increases or decreases in a same direction as the temperature increases or decreases.
4 . The method of claim 2 , wherein the ZTC current is invariable relative to temperature.
5 . The method of claim 1 , wherein regulating the instantaneous write voltage based on comparing the instantaneous write voltage with the temperature adjusted reference voltage comprises:
generating a third current based on comparing the instantaneous write voltage with the temperature adjusted reference voltage; and
sinking the third current in the bit line.
6 . A temperature compensation circuit comprising:
a reference voltage generator circuit, wherein the reference voltage generator circuit is configured to generate a temperature adjusted reference voltage based on a Proportional to Absolute Temperature (PTAT) current and a Zero Temperature Coefficient (ZTC) current; and
a voltage regulator circuit connected to the reference voltage generator circuit, wherein the voltage regulator circuit is configured to:
compare an instantaneous write voltage of a bit line of a memory device with the temperature adjusted reference voltage, and
regulate the instantaneous write voltage of the bit line based on the comparison, wherein the temperature compensation circuit is connectable to the bit line of the memory device.
7 . The temperature compensation circuit of claim 6 , wherein the reference voltage generator circuit comprises:
a first current source;
a second current source connected in parallel to the first current source at a reference node; and
a variable resistor connected between the reference node and ground, wherein the reference node is configured to provide the temperature adjusted reference voltage.
8 . The temperature compensation circuit of claim 7 , wherein the first current source is a PTAT current source and the second current source is a ZTC current source.
9 . The temperature compensation circuit of claim 8 , wherein a first current generated by the PTAT current source is proportional to temperature and increases or decreases in a same direction as the temperature increases or decreases.
10 . The temperature compensation circuit of claim 8 , wherein a second current generated by the ZTC current source is invariable relative to temperature.
11 . The temperature compensation circuit of claim 6 , wherein the voltage regulator circuit comprises an amplifier and a third current source, wherein the amplifier comprises a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the amplifier is connected to a reference voltage node, wherein the second input terminal of the amplifier is connected to the selected bit line, and wherein the output terminal of the amplifier is connected to the third current source.
12 . The temperature compensation circuit of claim 11 , wherein the amplifier is configured to regulate an amount of current sinked by the third current source to the selected bit line based on the comparing the instantaneous write voltage with the temperature compensated reference voltage.
13 . The temperature compensation circuit of claim 6 , further comprising a unigain buffer connected between the reference voltage generator circuit and the voltage regulator circuit.
14 . A voltage control circuit comprising:
a voltage detection circuit, wherein the voltage detection circuit detects an instantaneous supply voltage; and
a voltage source selection circuit connected to the voltage detection circuit, wherein the voltage source selection circuit is configured to select a voltage source from a plurality of voltage sources based on the detected instantaneous supply voltage, and wherein the voltage source selection circuit comprises a switch that connects the selected voltage source to a selected bit line of a memory device to provide a write voltage.
15 . The voltage control circuit of claim 14 , wherein the voltage source selection circuit being configured to select the voltage source from the plurality of voltage sources based on the detected instantaneous supply voltage comprises the voltage source selection circuit being configured to:
compare the instantaneous supply voltage with a reference voltage;
select the voltage source from the plurality of voltage sources based on comparison of the instantaneous supply voltage with the reference voltage.
16 . The memory device of claim 15 , wherein voltage source selection circuit is configured to select a first voltage source of the plurality of voltages sources when the instantaneous supply voltage is less than the reference voltage.
17 . The memory device of claim 15 , wherein voltage source selection circuit is configured to select a second voltage source of the plurality of voltages sources when the instantaneous supply voltage is more than the reference voltage.
18 . The memory device of claim 15 , wherein the voltage source selection circuit is configured to compare the instantaneous supply voltage with the reference voltage on expiry of a timer.
19 . The memory device of claim 14 , wherein the voltage source selection circuit further comprises a latch circuit, and wherein the latch circuit is configured to latch a comparison output of a comparator.
20 . The memory device of claim 19 , wherein the latch circuit is triggered by a clock signal, and wherein the clock signal is generated by a timer.