Bypass circuitry to improve switching speed
Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.
1 . A radio frequency (RF) switching circuit comprising:
a field effect transistor (FET) stack having multiple FETs;
drain-source resistive elements, each coupled between drain and source terminals of a corresponding FET; bypass switching elements coupled in parallel with corresponding drain-source resistive elements; and
a control circuit configured to generate timing signals for the bypass switching elements;
wherein the control circuit includes: a resistive element; and level shifting circuitry coupled to the bypass switching elements through the resistive element;
wherein the control circuit generates: a first timing signal for the bypass switching elements; and a second timing signal for the control FETs;
wherein the control circuit comprises: a delay element coupled to process at least one of the first and second timing signals; and a level shifter having multiple outputs with different timing relationships; and
wherein the bypass switching elements are configured to: remain in an OFF state when the FET stack is in a steady ON state or steady OFF state; and switch to an ON state only during transitions of the FET stack from the steady ON state to the steady OFF state.
2 . The RF switching circuit of claim 1 , wherein the control circuit comprises: multiple control FETs arranged in series; and resistive elements coupled across respective control FETs.
3 . The RF switching circuit of claim 1 , wherein the second timing signal begins after the first timing signal and has a shorter duration.
4 . The RF switching circuit of claim 1 , wherein the delay element is configured to:
receive an input control signal;
generate a delayed version of the input control signal for ON to OFF transitions; and
pass the input control signal without delay for OFF to ON transitions.
5 . A radio frequency (RF) switch comprising:
a primary switching section having series-connected FETs;
bypass paths connected across source-drain paths of the FETs;
a control section having: control transistors arranged in series;
a delay block coupled to the control section through a resistor and connected to an input voltage of the gates;
bypass elements across the control transistors; and
signal routing circuitry configured to:
maintain the bypass paths in an OFF state during steady ON and OFF states of the primary switching section; and
switch the bypass paths to an ON state during transitions from the steady ON state to the steady OFF state; and
the delay block configured to only delay an OFF state of the control section compared to the OFF state of the primary switching section.
6 . The RF switch of claim 5 , wherein the control section generates: a primary control signal for the bypass paths; and a secondary control signal for the control transistors.
7 . The RF switch of claim 6 , wherein the primary and secondary control signals have different timing relationships.
8 . The RF switch of claim 5 , further comprising: gate control circuitry coupled to gates of the series-connected FETs; and gate resistive elements between the gate control circuitry and the gates.
9 . The RF switch of claim 8 , wherein the gate control circuitry includes: gate bypass switches coupled in series; and a timing controller for the gate bypass switches.
10 . The RF switch of claim 9 , wherein the timing controller coordinates operation of the gate bypass switches with the bypass paths.
11 . A method of controlling switching speed in an RF switch, comprising:
providing a FET stack with drain-source resistive elements;
coupling bypass switches across the drain-source resistive elements;
initiating a transition of the FET stack from a conductive state to a non-conductive state;
activating the bypass switches for a predetermined duration during the transition;
maintaining the bypass switches active until the FET stack reaches a steady non- conductive state; deactivating the bypass switches when the FET stack is in the steady non- conductive state;
generating a first timing signal for the bypass switches;
generating a second timing signal for control elements in a control circuit;
processing the first timing signal through a delay element to create a transition- dependent delayed signal such that the transition-dependent delayed signal is only delayed during ON to OFF transitions of the FET stack.
12 . The method of claim 11 , wherein the second timing signal has a longer duration than the first timing signal.
13 . The method of claim 11 , further comprising: providing gate bypass switches coupled to gates of FETs in the FET stack; and coordinating activation of the gate bypass switches with the bypass switches during the transition.
14 . The method of claim 11 , further comprising: generating an inverted version of the first timing signal through a level shifter; and using the inverted version to control the bypass switches with opposite polarity timing.