RF branch with accelerated turn-on and high Q value
Improved Radio Frequency (RF) switches are provided herein. According to one aspect, an RF switch comprises one or more stages. In one embodiment, each stage comprises a signal input terminal, a signal output terminal, a control input terminal, and a switching device having a first terminal connected to the signal input terminal, a second terminal connected to the signal output terminal, and a third terminal for controlling the on/off state of the switching device. Each stage includes a first resistor connected in series between the control input terminal and the third terminal, a first bypass switch for electrically bypassing the first resistor, and a second resistor connected in series between the signal input terminal and the signal output terminal. The first resistors form a first bias network, the second resistors form a second bias network, and the switching devices are connected in series.
1. A radio frequency (RF) switch, comprising:
one or more stages, each stage comprising:
a signal input terminal;
a signal output terminal;
a control input terminal;
a switching device having a first terminal connected to the signal input terminal, a second terminal connected to the signal output terminal, and a third terminal for controlling an on/off state of the switching device;
a first resistor connected in series between the control input terminal and the third terminal;
a first bypass switch for connecting each end of the first resistor to bypass the first resistor when the first bypass switch is closed;
a second resistor connected in series between the signal input terminal and the signal output terminal; and
a second bypass switch for connecting each end of the second resistor to bypass the second resistor when the second bypass switch is closed;
wherein the first bypass switch and the second bypass switch are configured to close concurrently to collectively reduce a respective time constant set by the first resistor and the second resistor;
the one or more first resistors forming a first bias network and the one or more second resistors forming a second bias network.
2. The switch of claim 1 wherein for at least one stage, the first bypass switch operates to bypass the first resistor when the switching device is in the on state and does not operate to bypass the first resistor when the switching device is in the off state.
3. The switch of claim 1 wherein for at least one stage, the first bypass switch comprises a plurality of switching devices in series.
4. The switch of claim 1 wherein the second bypass switch operates to bypass the second resistor when the switching device is in the on state and does not operate to bypass the second resistor when the switching device is in the off state.
5. The switch of claim 1 wherein a control signal for the second bypass switch is derived from a control signal of the first bypass switch.
6. The switch of claim 1 wherein a control signal for the second bypass switch is independent from a control signal of the first bypass switch.
7. The switch of claim 1 wherein at least one stage further comprises at least one diode connected in series between the second terminal and the control input terminal to provide a discharge path from the second terminal to the control input terminal.
8. The switch of claim 7 wherein the second terminal is connected to an anode of one of the at least one diode and wherein the control input terminal is connected to a cathode of one of the at least one diode.
9. The switch of claim 1 wherein, for at least one stage, the switching device comprises a field-effect transistor (FET), the first terminal comprising a source terminal of the FET, the second terminal comprising a drain terminal of the FET, the third terminal comprising a gate terminal of the FET.
10. The switch of claim 9 wherein the FET further comprises a body terminal connected to the body of the FET.
11. The switch of claim 10 wherein at least one stage further comprises a first body switch for connecting the source terminal of the FET to the body terminal of the FET when closed and a second body switch for connecting the drain terminal of the FET to the body terminal of the FET when closed.
12. The switch of claim 11 wherein the first body switch comprises one or more switching devices in series.
13. The switch of claim 11 wherein the second body switch comprises one or more switching devices in series.
14. The switch of claim 10 wherein at least one stage further comprises a third body switch for connecting the gate terminal of the FET to the body terminal of the FET when closed.
15. The switch of claim 14 wherein the third body switch comprises one or more switching devices in parallel.
16. The switch of claim 11 wherein, for the at least one stage, the first body switch and the second body switch also operate as an acceleration network.
17. The switch of claim 1 wherein at least one stage further comprises at least one diode connected in series between a source terminal or a drain terminal and a body terminal to provide a discharge path from the source terminal or drain terminal to the body terminal.
18. The switch of claim 1 comprising a plurality of the stages, wherein the switching devices of the plurality of stages are connected in series.
19. The switch of claim 1 further providing a pulsed control signal to the third terminal of at least one stage, wherein the pulsed control signal is not active for all of the time that the switching device is on.