Flush-on-demand processor instruction trace
In a general aspect, a processor can include an instruction processing unit configured to execute a plurality of machine-readable instructions of a program in accordance with a control flow of the program and, in response to completing execution of respective instructions of the machine-readable instructions, produce respective instruction retirement information. The processor can also include a selectively enablable trace encoder that is configured, when enabled, to receive the respective instruction retirement information, and encode the instruction retirement information in an instruction trace corresponding with the control flow. The processor can also include a circular buffer that is configured to, when the trace encoder is enabled, receive and store the instruction trace, and, in response to a flush, communicate the stored instruction trace via a memory interface, where the memory interface is selectively enabled in response to the flush request.
1 . A processor comprising:
an instruction processing unit configured to:
execute a plurality of machine-readable instructions of a program in accordance with a control flow of the program, and
produce respective instruction retirement information for each of the plurality of machine-readable instructions;
a trace encoder that is selectively enablable, wherein the trace encoder is configured to:
receive the respective instruction retirement information, and
encode the respective instruction retirement information in an encoded instruction trace corresponding with the control flow of the program; and
a circular buffer that is configured to:
receive the encoded instruction trace from the trace encoder; and
store the encoded instruction trace; and
wherein the processor is configured to:
enable the trace encoder;
disable a memory interface while the trace encoder is enabled;
receive a flush request; and
enable the memory interface in response to the flush request, wherein the encoded instruction trace stored in the circular buffer is communicated over the memory interface.
2 . The processor of claim 1 , further comprising a configuration register operatively coupled with at least one of the trace encoder or the memory interface, the configuration register including at least one configuration bit configured to:
selectively enable and disable the trace encoder; and
selectively enable and disable the memory interface.
3 . The processor of claim 2 , wherein the at least one configuration bit includes a configuration bit that can have a first logic value or a second logic value, the processor being configured to:
when the configuration bit has the first logic value, enable the trace encoder and disable the memory interface; and
when the configuration bit has the second logic value, disable the trace encoder and enable the memory interface.
4 . The processor of claim 2 , wherein the at least one configuration bit includes:
a first configuration bit to selectively enable and disable the trace encoder; and
a second configuration bit to selectively enable and disable the memory interface.
5 . The processor of claim 1 , wherein the respective instruction retirement information includes at least one of:
a program counter value;
an indication of an instruction type; or
an indication of an instruction result.
6 . The processor of claim 1 , wherein the trace encoder is configured, when encoding the respective instruction retirement information of the encoded instruction trace, to periodically communicate synchronization packets to, and for storage in, the circular buffer,
a synchronization packet of the synchronization packets including a respective program counter value indicating a starting executable instruction address of the encoded instruction trace subsequent to the synchronization packet.
7 . The processor of claim 6 , wherein periodically communicating synchronization packets includes periodically communicating synchronization packets such that a first synchronization packet is stored at a beginning of the circular buffer, and a second synchronization packet is stored at a mid-point of the circular buffer.
8 . The processor of claim 6 , wherein periodically communicating synchronization packets includes periodically communicating synchronization packets such that the circular buffer, when filled with information of the encoded instruction trace, includes two or more sync packets.
9 . The processor of claim 6 , wherein periodically communicating synchronization packets includes periodically communicating synchronization packets based on a number of instruction trace packets provided to the circular buffer by the trace encoder.
10 . The processor of claim 6 , wherein periodically communicating synchronization packets includes periodically communicating synchronization packets based on a number of instructions encoded in the encoded instruction trace since communication of a previous synchronization packet.
11 . The processor of claim 6 , wherein a size of the circular buffer is based on a number of instructions to be encoded in the encoded instruction trace after a corresponding synchronization packet.
12 . The processor of claim 1 , wherein storing the encoded instruction trace includes, when an end of the circular buffer is reached, overwriting previously stored encoded instruction trace starting at a beginning of the circular buffer.
13 . The processor of claim 1 , wherein encoding the respective instruction retirement information in the encoded instruction trace includes:
encoding:
instruction retirement information for non-sequential machine-readable instructions with respective destinations that cannot be inferred from the program, and
instruction retirement information for conditionally non-sequential machine-readable instructions; and
excluding encoding instruction retirement information for sequential machine-readable instructions from the encoded instruction trace.
14 . The processor of claim 13 , wherein encoded instruction information for a conditionally non-sequential instruction includes a single bit indicating whether or a not a branch in the control flow of the program was taken.
15 . The processor of claim 1 , wherein the memory interface is always disabled while the trace encoder is enabled.
16 . A system comprising:
a processor including:
an instruction processing unit configured to:
execute a plurality of machine-readable instructions of a program in accordance with a control flow of the program, and
produce respective instruction retirement information for each of the plurality of machine-readable instructions;
a trace encoder that is selectively enablable, wherein the trace encoder is configured to:
receive the respective instruction retirement information, and
encode the respective instruction retirement information in an encoded instruction trace corresponding with the control flow of the program; and
a circular buffer that is configured to:
receive the encoded instruction trace from the trace encoder; and
store the encoded instruction trace;
wherein the processor is configured to:
enable the trace encoder;
disable a memory interface while the trace encoder is enabled;
receive a flush request; and
enable the memory interface in response to the flush request, wherein the encoded instruction trace stored in the circular buffer is communicated over the memory interface;
memory operationally coupled with the memory interface, the memory being configured to receive and save the encoded instruction trace received via the memory interface; and
a decoder configured to, based on the plurality of machine-readable instructions of the program and the encoded instruction trace received via the memory interface, reconstruct the control flow of the program.
17 . The system of claim 16 , wherein the circular buffer is implemented using one of:
an array of digital-logic gates;
a cache memory of the processor; or
a static-random-access memory of the processor.
18 . The system of claim 16 , wherein the decoder is implemented on a computing system operationally coupled with the memory to obtain the encoded instruction trace received via the memory interface,
the computing system having the plurality of machine-readable instructions of the program stored therein, or having access to the plurality of machine-readable instructions of the program via a communication interface.
19 . A method for operating a processor, the method comprising:
receiving, by the processor, a request to enable an instruction trace mode of operation;
in response to receiving the request to enable the instruction trace mode of operation:
disabling a memory interface configured to communicate an instruction trace produced by a trace encoder to memory;
executing, by an instruction processing unit of the processor, a plurality of machine-readable instructions of a program in accordance with a control flow of the program;
producing, by the instruction processing unit for each of the plurality of machine-readable instructions, respective instruction retirement information;
receiving, by the trace encoder, the respective instruction retirement information;
encoding, by the trace encoder, the respective instruction retirement information in the instruction trace in correspondence with the control flow of the program;
sending, by the trace encoder, the instruction trace to a circular buffer of the processor;
storing, by the circular buffer, the instruction trace received from the trace encoder;
receiving, by the processor, a request to flush the instruction trace stored in the circular buffer; and
in response to receiving the request to flush the instruction trace stored in the circular buffer:
enabling the memory interface; and
communicating the instruction trace stored in the circular buffer from the circular buffer to the memory via the memory interface.
20 . The method of claim 19 , further comprising, when encoding the instruction trace, periodically communicating synchronization packets to, and for storage in, the circular buffer,
a synchronization packet of the synchronization packets including a respective program counter value indicating a starting executable instruction address for instruction trace subsequent to the synchronization packet.
21 . The method of claim 20 , wherein periodically communicating synchronization packets includes periodically communicating synchronization packets such that a first synchronization packet is stored at a beginning of the circular buffer, and a second synchronization packet is stored at mid-point of the circular buffer.
22 . The method of claim 19 , wherein encoding the respective instruction retirement information in the instruction trace includes:
encoding, in the instruction trace:
instruction retirement information for non-sequential machine-readable instructions, and
instruction retirement information for conditionally non-sequential machine-readable instructions; and
excluding encoding instruction retirement information for sequential machine-readable instructions from the instruction trace.
23 . The method of claim 22 , wherein encoded instruction information for a conditionally non-sequential instruction includes a single bit indicating whether or a not a branch in the control flow of the program was taken.