Semiconductor device
A semiconductor device includes a substrate including a peripheral active pattern defined by a device isolation layer, a gate structure on the peripheral active pattern, and a gate spacer covering at least a portion of a side surface of the gate structure. The gate structure includes an insulating pattern structure and a metal pattern structure on the insulating pattern structure. The insulating pattern structure includes a recess having a maximum depth in a first direction parallel to a top surface of the substrate at a first height. The insulating pattern structure includes a first gate insulating pattern and a high-k dielectric layer, which are sequentially stacked on the top surface of the substrate. The gate spacer includes a protrusion inserted in the recess.
1 . A semiconductor device comprising:
a substrate including a peripheral active pattern defined by a device isolation layer;
a gate structure on the peripheral active pattern; and
a gate spacer covering at least a portion of a side surface of the gate structure,
wherein the gate structure comprises an insulating pattern structure and a metal pattern structure on the insulating pattern structure,
wherein the insulating pattern structure includes a recess having a maximum depth in a first direction parallel to a top surface of the substrate at a first height,
wherein the insulating pattern structure comprises a first gate insulating pattern and a high-k dielectric layer, which are sequentially stacked on the top surface of the substrate, and wherein the gate spacer includes a protrusion in the recess,
wherein the first height is higher than a height of an upper surface of the first gate insulating pattern.
2 . The semiconductor device of claim 1 , wherein the insulating pattern structure further comprises a second gate insulating pattern between the first gate insulating pattern and the high-k dielectric layer,
wherein the second gate insulating pattern and the first gate insulating pattern include different insulating materials, and
wherein the recess is located between a bottom surface of the second gate insulating pattern and a top surface of the high-k dielectric layer.
3 . The semiconductor device of claim 2 , further comprising:
a first spacer, a second spacer, and a third spacer, which are sequentially stacked on the gate spacer,
wherein the gate spacer and the second spacer include a first material,
wherein the first spacer and the third spacer include a second material, and
wherein the first material and the second material are different from each other.
4 . The semiconductor device of claim 2 , wherein the first gate insulating pattern extends in the first direction, and
wherein the gate spacer further extends onto a top surface of the first gate insulating pattern.
5 . The semiconductor device of claim 2 , wherein the first gate insulating pattern includes silicon oxynitride,
wherein the second gate insulating pattern includes silicon oxide, and
wherein the high-k dielectric layer includes a high-k dielectric material.
6 . The semiconductor device of claim 1 , wherein the metal pattern structure comprises a first conductive pattern, a gate pattern, a barrier pattern, and a metal-containing pattern, which are sequentially stacked, and
wherein the recess extends from a bottom surface of the high-k dielectric layer to a top surface of the first conductive pattern.
7 . The semiconductor device of claim 6 , wherein the metal pattern structure further comprises a second conductive pattern disposed between the first conductive pattern and the gate pattern,
wherein the first conductive pattern includes a metal having a P work function, and
wherein the second conductive pattern includes a metal having an N work function.
8 . The semiconductor device of claim 1 , wherein the insulating pattern structure further comprises a second gate insulating pattern between the first gate insulating pattern and the high-k dielectric layer, and
wherein an edge portion of a top surface of the first gate insulating pattern is exposed from the second gate insulating pattern to an outside.
9 . The semiconductor device of claim 8 , wherein the metal pattern structure comprises a first conductive pattern, a second conductive pattern, a gate pattern, a barrier pattern and a metal-containing pattern, which are sequentially stacked, and
wherein the recess extends from a bottom surface of the high-k dielectric layer to a top surface of the second conductive pattern.
10 . The semiconductor device of claim 1 , wherein the insulating pattern structure further comprises a second gate insulating pattern disposed between the first gate insulating pattern and the high-k dielectric layer,
wherein the second gate insulating pattern and the first gate insulating pattern include different insulating materials,
wherein the metal pattern structure comprises a first conductive pattern,
wherein the first conductive pattern has a P work function, and
wherein the recess extends from a bottom surface of the second gate insulating pattern to a top surface of the first conductive pattern.
11 . The semiconductor device of claim 1 , wherein the recess is located between a bottom surface of the first gate insulating pattern and a bottom surface of the high-k dielectric layer.
12 . The semiconductor device of claim 1 , wherein the insulating pattern structure further comprises a second gate insulating pattern disposed between the first gate insulating pattern and the high-k dielectric layer,
wherein the metal pattern structure comprises a first conductive pattern, a second conductive pattern, a gate pattern, a barrier pattern, and a metal-containing pattern, which are sequentially stacked,
wherein the first gate insulating pattern and the second gate insulating pattern include different insulating materials,
wherein the first conductive pattern and the second conductive pattern include different metals,
wherein a side surface of the gate pattern, a side surface of the barrier pattern, and a side surface of the metal-containing pattern are aligned with each other, and
wherein the recess extends from a bottom surface of the first gate insulating pattern to a top surface of the second conductive pattern.
13 . A semiconductor device comprising:
a substrate including a peripheral active pattern defined by a device isolation layer;
a gate structure on the peripheral active pattern;
a gate spacer covering at least a portion of a side surface of the gate structure;
a lower insulating pattern provided on the substrate and covering the gate structure and the gate spacer; and
a contact plug laterally spaced apart from the gate structure and penetrating the lower insulating pattern so as to be connected to the substrate,
wherein the gate structure comprises an insulating pattern structure and a metal pattern structure on the insulating pattern structure,
wherein the insulating pattern structure includes a recess having a maximum depth in a first direction parallel to a top surface of the substrate at a first height,
wherein a distance from a side surface of the contact plug to a side surface of the metal pattern structure is a first distance,
wherein a distance from the side surface of the contact plug to a bottom surface of the recess is a second distance, and
wherein the second distance is greater than the first distance.
14 . The semiconductor device of claim 13 , wherein the second distance is in a range of about 30 nm to about 100 nm.
15 . The semiconductor device of claim 13 , wherein the insulating pattern structure comprises a first gate insulating pattern and a high-k dielectric layer on the first gate insulating pattern, and
wherein the recess is located between a bottom surface of the first gate insulating pattern and a top surface of the high-k dielectric layer.
16 . The semiconductor device of claim 13 , further comprising:
a diffusion barrier pattern disposed between the lower insulating pattern and the contact plug,
wherein the diffusion barrier pattern includes a metal nitride.
17 . The semiconductor device of claim 13 , further comprising:
a first spacer covering the gate structure and the gate spacer and extending onto the top surface of the substrate; and
a second spacer and a third spacer, which are sequentially stacked on the first spacer,
wherein the gate spacer and the second spacer include silicon nitride,
wherein the first spacer and the third spacer include silicon oxide, and
wherein the contact plug further penetrates the first spacer, the second spacer, and the third spacer.
18 . The semiconductor device of claim 13 , wherein the insulating pattern structure comprises a first gate insulating pattern, a second gate insulating pattern and a high-k dielectric layer, which are sequentially stacked,
wherein a distance from the side surface of the contact plug to a side surface of the first gate insulating pattern is a third distance, and
wherein the third distance is less than the first distance and the second distance.
19 . A semiconductor device comprising:
a substrate including cell active patterns on a cell region and a peripheral active pattern on a peripheral region around the cell region;
word lines provided in the substrate and intersecting the cell active patterns;
bit lines provided on the substrate and intersecting the word lines;
a bit line contact provided on a central portion of each of the cell active patterns and connected to a corresponding one of the bit lines;
a storage node contact on each of both end portions of each of the cell active patterns;
a landing pad on the storage node contact;
a capacitor on the landing pad;
a gate structure on the peripheral active pattern; and
a gate spacer covering at least a portion of a side surface of the gate structure,
wherein the gate structure comprises an insulating pattern structure and a metal pattern structure on the insulating pattern structure,
wherein the insulating pattern structure includes a recess having a maximum depth in a first direction parallel to a top surface of the substrate at a first height, and
wherein the gate spacer comprises a protrusion inserted in the recess.
20 . The semiconductor device of claim 19 , wherein the gate spacer is spaced apart from the substrate.