Systems, apparatuses, and methods for addition of partial products
Embodiments of systems, apparatuses, and methods for fused multiple add. In some embodiments, a decoder decodes a single instruction having an opcode, a destination field representing a destination operand, and fields for a first, second, and third packed data source operand, wherein packed data elements of the first and second packed data source operand are of a first, different size than a second size of packed data elements of the third packed data operand. Execution circuitry then executes the decoded single instruction to perform, for each packed data element position of the destination operand, a multiplication of a M N-sized packed data elements from the first and second packed data sources that correspond to a packed data element position of the third packed data source, add of results from these multiplications to a full-sized packed data element of a packed data element position of the third packed data source, and storage of the addition result in a packed data element position destination corresponding to the packed data element position of the third packed data source, wherein M is equal to the full-sized packed data element divided by N.
1. An apparatus comprising:
a decoder to decode a single instruction having an opcode field and four operand fields, the four operand fields comprising:
a first operand field to indicate a first source packed data register, the first source packed data register to store first source packed data elements,
a second operand field to indicate a second source packed data register, the second source packed data register to store second source packed data elements,
a third operand field to indicate a source and destination (source/destination) packed data register, the source/destination packed data register to store third source packed data elements and result packed data elements, and
a fourth operand field to indicate a writemask register, the writemask register to store a plurality of bit values to conditionally control per-element operations indicated by the single instruction;
wherein the first and second source packed data elements are data elements of a first size, different than a second size of the third source packed data elements and the result packed data elements;
a register file including the first source packed data register, the second source packed data register, and the source/destination packed data register; and
execution circuitry to execute the decoded single instruction to, for each result packed data element:
preserve an existing value of the result packed data element or set the result packed data element to zero if a corresponding bit value in the writemask register is set to a first value; and
if the corresponding bit value in the writemask register is set to a second value, then:
multiply a first number of the first source packed data elements with corresponding packed data elements of the second source packed data elements to produce a first number of products,
add the first number of products to a corresponding packed data element from the third source packed data elements to produce the result packed data element of the second size in a corresponding position in the source/destination packed data register.
2. The apparatus of claim 1 wherein the first number is equal to the second size divided by the first size.
3. The apparatus of claim 1 wherein the first value comprises a value of 0 and the second value comprises a value of 1.
4. The apparatus of claim 1 wherein the result packed data elements comprise packed 32-bit floating-point values.
5. The apparatus of claim 1 wherein the first size and the second size are based on an opcode value.
6. The apparatus of claim 1 , wherein the first size is half or a quarter of the second size.
7. The apparatus of claim 1 , wherein the register file further includes the writemask register.