Parallel-type Tx/Rx concurrent impedance matching utilizing Rx mutual inductance matching
An apparatus including: a transmitter output impedance matching circuit including an inductive element; a low noise amplifier (LNA) including a first field effect transistor (FET); a receiver input impedance matching circuit, including: a transformer including a first winding and a second winding; and a capacitor coupled in series with the first winding between a first end of the inductive element and a gate of the first FET, wherein the second winding is coupled to a second end of the inductive element; and a radio frequency (RF) port coupled between the first end of the inductive element and the capacitor.
1 . An apparatus, comprising:
a transmitter output impedance matching circuit including an inductive element;
a low noise amplifier (LNA) comprising a first field effect transistor (FET);
a receiver input impedance matching circuit, comprising:
a transformer including a first winding and a second winding; and
a capacitor coupled in series with the first winding between a first end of the inductive element and a gate of the first FET, wherein the second winding is coupled to a second end of the inductive element; and
a radio frequency (RF) port coupled between the first end of the inductive element and the capacitor.
2 . The apparatus of claim 1 , wherein the first and second windings are in an opposite polarity configuration.
3 . The apparatus of claim 2 , wherein the transformer further comprises a third winding coupled between a source of the first FET and a ground terminal, and wherein the second winding is coupled between the second end of the inductive element and the ground terminal.
4 . The apparatus of claim 3 , wherein the first and third windings are in opposite polarity configuration.
5 . The apparatus of claim 1 , wherein the second winding comprises a tap coupled to a ground terminal.
6 . The apparatus of claim 5 , wherein the tap separates first and second sub-windings of the second winding.
7 . The apparatus of claim 1 , further comprising a switching device coupled between the second end of the inductive element and a ground terminal.
8 . The apparatus of claim 7 , wherein a closed or open state of the switching device is responsive to a mode signal indicating a transmit or receive mode, respectively.
9 . The apparatus of claim 1 , further comprising a switching device coupled between a node, between the capacitor and the first winding, and a ground terminal.
10 . The apparatus of claim 9 , wherein a closed or open state of the switching device is responsive to a mode signal indicating a transmit or receive mode, respectively.
11 . The apparatus of claim 1 , wherein the transmitter output impedance matching circuit comprises a balun including a primary winding and a secondary winding, wherein the inductive element comprises the secondary winding.
12 . The apparatus of claim 11 , wherein the inductive element further comprises an inductor coupled in parallel with the secondary winding.
13 . The apparatus of claim 11 , further comprising a power amplifier (PA) including differential outputs coupled to ends of the primary winding of the balun, respectively.
14 . The apparatus of claim 1 , further comprising at least one antenna coupled to the RF port.
15 . The apparatus of claim 1 , wherein the LNA further comprises a second FET coupled between an output of the LNA and the first FET, wherein the second FET includes a gate configured to receive a cascode bias voltage.
16 . The apparatus of claim 1 , further comprising:
one or more frequency downconverting stages coupled to an output of the LNA; and
at least one clock source coupled to the one or more frequency downconverting stages.
17 . The apparatus of claim 16 , further comprising an analog-to-digital converter (ADC) coupled to an output of the one or more frequency downconverting stages, wherein the at least one clock source is coupled to the ADC.
18 . The apparatus of claim 17 , further comprising a modem coupled to an output of the ADC, wherein the at least one clock source is coupled to the modem.
19 . The apparatus of claim 1 , further comprising a power amplifier (PA) including an output coupled to the transmitter output impedance matching circuit.
20 . The apparatus of claim 19 , further comprising:
one or more frequency upconverting stages coupled to an input of the PA; and
at least one clock source coupled to the one or more frequency upconverting stages.
21 . The apparatus of claim 20 , further comprising a digital-to-analog converter (DAC) coupled to an input of the one or more frequency upconverting stages.
22 . The apparatus of claim 19 , further comprising an ultra-wideband (UWB) pulse shaping circuit coupled to an input of a digital-to-analog converter (DAC), wherein the DAC includes an output coupled to the PA, and wherein at least one clock source is coupled to the UWB pulse shaping circuit and the DAC.