Low-power block code forward error correction decoder
A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.
1 . A system comprising:
a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry, wherein:
the key-equation solver circuitry comprises an array of processing elements arranged in columns and rows, and
the key-equation solver circuitry is dynamically configurable to vary a first number of the rows and a second number of the columns in the array of processing elements to decode a codeword based on:
a third number of syndromes associated with the codeword to be computed, wherein the first number is greater than or equal to twice the third number, and
conditions of a channel over which the codeword was received.
2 . The system of claim 1 , wherein:
the syndrome computation circuitry comprises a plurality of syndrome compute units connected in parallel; and
each of the syndrome compute units comprises a plurality of adders, a plurality of multipliers, and a plurality of memory elements.
3 . The system of claim 1 , wherein:
the syndrome computation circuitry is operable to use a first quantity of the processing elements for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the processing elements for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate; and
the first quantity of the processing elements is greater than the second quantity of the processing elements and the first bit error rate is greater than the second bit error rate.
4 . The system of claim 1 , each of the processing elements of the key-equation solver circuitry comprises a plurality of multipliers, one or more adder, one or more memory elements, and one or more multiplexers.
5 . The system of claim 1 , wherein:
the search and evaluator circuitry comprises a plurality of processing units connected in parallel; and
the search and evaluator circuitry is dynamically configurable to vary a quantity of the processing units of the search and evaluator circuitry used for processing of a codeword based on conditions of a channel over which the codeword was received.
6 . The system of claim 5 , wherein each of the processing units of the search and evaluator circuitry comprises a plurality of multipliers, one or more multiplexer, and one or more memory element.
7 . The system of claim 5 , wherein:
the search and evaluator circuitry is operable to use a first quantity of the processing units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the processing units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate; and
the first quantity of the processing units of the search and evaluator circuitry is greater than the second quantity of the processing units of the search and evaluator circuitry and the first bit error rate is greater than the second bit error rate.
8 . The system of claim 1 , wherein the key-equation solver circuitry determines an error locator polynomial to find a location of an error symbol in the codeword and an error evaluator polynomial to calculate a value of the error symbol in the codeword based on the conditions of the channel.
9 . The system of claim 1 , wherein the second number is equal to one plus three times the third number.
10 . The system of claim 1 , wherein the processing elements are implemented on time-shared hardware.
11 . A method, comprising:
in a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry, wherein the key-equation solver circuitry comprises an array of processing elements arranged in columns and rows:
dynamically determining a quantity of the processing elements and an arrangement of a first number of columns and a second number of rows of the processing elements to use for decoding a codeword, wherein the determining is based on a third number of syndromes associated with the codeword to be computed and conditions of a channel over which the codeword was received, wherein the first number is greater than or equal to twice the third number; and
decoding the codeword using the determined quantity of processing elements.
12 . The method of claim 11 , wherein the syndrome computation circuitry comprises a plurality syndrome compute units that each comprise a plurality of adders, a plurality of multipliers, and a plurality of memory elements.
13 . The method of claim 11 , wherein:
the codeword is received over the channel when the channel is characterized by a first bit error rate;
the decoding uses a first quantity of syndrome compute units;
a second codeword is received over the channel when the channel is characterized by a second bit error rate;
the method comprises dynamically determining to use a second quantity of syndrome compute units for decoding the second codeword;
the first bit error rate is greater than the second bit error rate;
the first quantity of syndrome compute units is greater than the second quantity of syndrome compute units; and
the method comprises decoding the second codeword using the second quantity of syndrome compute units.
14 . The method of claim 11 , each of the processing elements of the key-equation solver circuitry comprises a plurality of multipliers, one or more adder, one or more memory elements, and one or more multiplexers.
15 . The method of claim 11 , wherein:
the search and evaluator circuitry comprises a plurality of processing units connected in parallel; and
the search and evaluator circuitry is dynamically configurable to vary how many of the processing units are used for processing of a codeword based on conditions of a channel over which the codeword was received.
16 . The method of claim 15 , wherein each of the processing units of the search and evaluator circuitry comprises a plurality of multipliers, one or more multiplexer, and one or more memory element.
17 . The method of claim 15 , wherein:
the codeword is received over the channel when the channel is characterized by a first bit error rate;
the decoding uses a first quantity of processing units of the search and evaluator circuitry;
a second codeword is received over the channel when the channel is characterized by a second bit error rate;
the method comprises dynamically determining to use a second quantity of processing units of the search and evaluator circuitry for decoding the second codeword;
the first bit error rate is greater than the second bit error rate;
the first quantity of processing units of the search and evaluator circuitry is greater than the second quantity of processing units of the search and evaluator solver circuitry; and
the method comprises decoding the second codeword using the second quantity of processing units of the search and evaluator circuitry.
18 . The method of claim 11 , further comprising determining an error locator polynomial to find a location of an error symbol in the codeword and an error evaluator polynomial to calculate a value of the error symbol in the codeword based on the conditions of the channel.
19 . The method of claim 11 , wherein the second number is equal to one plus three times the third number.
20 . The method of claim 11 , wherein the processing elements are implemented on time-shared hardware.