Decoder for low-density parity-check convolutional codes

1. A processor to facilitate decoding of arbitrary length blocks of low-density, parity-check codes, the processor comprising:

a plurality of interconnected nodes; and

a memory interconnected with the plurality of interconnected nodes, the memory adapted to store intermediate log likelihood ratio (LLR) values based on channel LLR values representing the low-density, parity-check codes to enable outputting LLR values having improved accuracy relative to the channel LLR values;

wherein the memory is adapted to store the intermediate LLR values in a circular buffer where a pointer tracks a current position in the circular buffer.

2. The processor of claim 1 wherein the memory further comprises a random access memory (RAM) device.

3. The processor of claim 2 wherein the RAM device further comprises multi-port RAM.

4. The processor of claim 3 further comprising a storage device to generate a predetermined plurality of addresses for reading and writing the intermediate LLR values.

5. The processor of claim 4 wherein the storage device comprises a read only memory (ROM) device.

6. The processor of claim 2 wherein the processor is further adapted to implement memory partitioning within the RAM device.

7. The processor of claim 6 further comprising a storage device to generate a predetermined plurality of addresses for reading and writing the intermediate LLR values to the RAM device.

8. The processor of claim 7 wherein the storage device comprises a read only memory (ROM) device.

9. The processor of claim 1 wherein the plurality of interconnected nodes further comprise:

a plurality of variable nodes, at least one of the plurality of variable nodes operable to process an oldest intermediate LLR value from the circular buffer; and

a parity-check node operable to supply a parity-check output LLR value to the circular buffer.

10. The processor of claim 1 wherein the pointer moves to a next address in the circular buffer at a rate of one address per buad period.

11. The processor of claim 1 wherein, at each time (t), the pointer defines an address in the circular buffer to which input LLR values for the processor at the time (t) are written.

12. The processor of claim 11 wherein the plurality of interconnected nodes further comprise a parity-check node adapted to:

read, at a time (t), a plurality of input LLR values from a plurality of addresses in the circular buffer defined by a plurality of predefined offsets from the address in the circular buffer defined by the pointer at the time (t);

process the plurality of input LLR values to provide a plurality of adjusted LLR values; and

write the plurality of adjusted LLR values back to the same plurality of addresses in the circular buffer.

13. A decoder for information bits represented by arbitrary length blocks of low-density, parity-check codes, the decoder comprising a plurality of interconnected processors, at least one of the plurality of interconnected processors further comprising:

a plurality of interconnected nodes; and

a memory interconnected with the plurality of interconnected nodes, the memory adapted to store intermediate log likelihood ratio (LLR) values based on channel LLR values representing the low-density, parity-check codes to enable outputting LLR values having improved accuracy relative to the channel LLR values, wherein the memory is adapted to store the intermediate LLR values in a circular buffer where a pointer tracks a current position in the circular buffer;

wherein final LLR values from one of the plurality of interconnected processors can be used to decision the information bits.

14. The decoder of claim 13 wherein the memory further comprises a random access memory (RAM) device.

15. The decoder of claim 14 wherein the plurality of interconnected nodes further comprise:

a plurality of variable nodes, at least one of the plurality of variable nodes operable to process an oldest intermediate LLR value from the circular buffer; and

a parity-check node operable to supply a parity-check output LLR value to the circular buffer.

16. The decoder of claim 15 wherein the RAM device further comprises multi-port RAM.

17. The decoder of claim 16 further comprising a storage device to generate a predetermined plurality of addresses for reading and writing the intermediate LLR values.

18. The decoder of claim 17 wherein the storage device comprises a read only memory (ROM) device.

19. The decoder of claim 15 wherein the one of the plurality of interconnected processors is further adapted to implement memory partitioning within the RAM device.

20. The decoder of claim 19 further comprising a storage device to generate a predetermined plurality of addresses for reading and writing the intermediate LLR values to the RAM device.

21. The decoder of claim 20 wherein the storage device comprises a read only memory (ROM) device.

22. The decoder of claim 13 wherein the pointer moves to a next address in the circular buffer at a rate of one address per buad period.

23. The decoder of claim 13 wherein, at each time (t), the pointer defines an address in the circular buffer to which input LLR values for the at least one of the plurality of interconnected processors at the time (t) are written.

24. The decoder of claim 23 wherein the plurality of interconnected nodes further comprise a parity-check node adapted to:

read, at a time (t), a plurality of input LLR values from a plurality of addresses in the circular buffer defined by a plurality of predefined offsets from the address in the circular buffer defined by the pointer at the time (t);

process the plurality of input LLR values to provide a plurality of adjusted LLR values; and

write the plurality of adjusted LLR values back to the same plurality of addresses in the circular buffer.

25. A method of processing information represented by arbitrary length blocks of low-density, parity-check codes, the method comprising:

passing a plurality of channel log likelihood ratio (LLR) values representing the information through a decoder comprising a plurality of processors;

alternately passing each of a plurality of intermediate LLR values through a variable node and a parity-check node, at least in part by storing the plurality of intermediate LLR values in and retrieving the plurality of intermediate LLR values from a memory device in each processor of the plurality of processors, wherein the memory device is adapted to store the plurality of intermediate LLR values in a circular buffer where a pointer tracks a current position in the circular buffer; and

decisioning the information based on output LLR values from at least one of the plurality of processors.

26. The method of claim 25 wherein the storing of the plurality of intermediate LLR values in and the retrieving the plurality of intermediate LLR values from the memory device each further comprises accessing the circular buffer within the memory device.

27. The method of claim 26 wherein the accessing of the circular buffer further comprises applying an address generated by a storage device.

28. The method of claim 27 wherein the storage device is pre-programmed, changeable, read only memory (ROM).

29. The method of claim 25 wherein at least one of the storing of the plurality of intermediate LLR values and the retrieving of the plurality of intermediate LLR values further comprises applying an address generated by a storage device.

30. The method of claim 29 wherein the storage device is pre-programmed, changeable, read only memory (ROM).

31. The method of claim 25 wherein the pointer moves to a next address in the circular buffer at a rate of one address per buad period.

32. The method of claim 25 wherein, at each time (t), the pointer defines an address in the circular buffer to which input LLR values for the processor at the time (t) are written.