IP Library Granted Patent US 12,393,247
Granted Patent B2
US 12,393,247 · App. 18/462,829 · Granted Aug 19, 2025

Multi-node system and power supply control method

Inventor: Tsubasa Matsushita (Tokyo, JP)
Assignee: Hitachi Vantara, Ltd.
G06F1/305G06F1/3225G06F1/30
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,393,247
App. No.
18/462,829
Granted
Aug 19, 2025
Kind
B2
Abstract

In the event of a partial outage, a multi-node system is enabled to start processing easily and appropriately. The multi-node system includes multiple nodes each including at least one controller, the controller including a processor, a power supply control microcomputer, a memory, and a nonvolatile memory. The processor detects whether or not any one of the nodes is inactive due to a power outage. The processor determines whether or not operation of the multi-node system can be continued, on the basis of operational status of the nodes. Upon determination that the operation of the multi-node system cannot be continued, the processor saves necessary data held in the memory into the nonvolatile memory. The power supply control microcomputer restarts the processor. When the node in the power outage has recovered therefrom following the restart, the multi-node system is caused to start processing.

Claims (22)

1. A multi-node system comprising:

a plurality of nodes each including at least one controller,

the controller including a processor, a power supply control device configured to control supply of power to the controller, a volatile memory, and a nonvolatile memory,

wherein the processor detects whether or not any one of the nodes is inactive due to a power outage,

the processor determines whether or not operation of the multi-node system can be continued, based on comparing a performance of processing by the multi-node system to a predetermined performance level,

upon determination that the operation of the multi-node system cannot be continued, the processor saves necessary data held in the volatile memory into the nonvolatile memory,

the power supply control device restarts the processor, and,

when the node in the power outage has recovered therefrom following the restart, the multi-node system is caused to start processing.

2. The multi-node system according to claim 1 , wherein the controller of some of the plurality of nodes stores control information necessary for continuing the operation of the multi-node system.

3. The multi-node system according to claim 2 , wherein, when all nodes that store the control information are inactive, the processor determines that the operation of the multi-node system cannot be continued.

4. The multi-node system according to claim 1 ,

wherein each of the nodes has a plurality of communicable paths, and,

when all the paths of any one of the nodes become non-communicable, the processor detects that the node is inactive due to the power outage.

5. The multi-node system according to claim 1 , wherein, after the multi-node system is caused to start processing, the processor causes outputting of a message indicating automatic recovery from a partial outage.

6. A power supply control method for use with a multi-node system having a plurality of nodes each including at least one controller,

the controller including a processor, a power supply control device configured to control supply of power to the controller, a volatile memory, and a nonvolatile memory,

the power supply control method comprising:

causing the processor to detect whether or not any one of the nodes is inactive due to a power outage;

causing the processor to determine whether or not operation of the multi-node system can be continued, based on comparing a performance of processing by the multi-node system to a predetermined performance level;

upon determination that the operation of the multi-node system cannot be continued, causing the processor to save necessary data held in the volatile memory into the nonvolatile memory;

causing the power supply control device to restart the processor; and,

when the node in the power outage has recovered therefrom following the restart, causing the multi-node system to start processing.

Assignments (2)
MERGER Recorded Aug 26, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 068393/0234 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2023
From: MATSUSHITA, TSUBASA
To: HITACHI, LTD.
Reel/Frame 064830/0733 →
Priority Claims (1)
JP 2022-212295 · Dec 28, 2022 · national
Continuity (1)
Related Publication 20240219986A1 · Jul 4, 2024
References Cited (16)
US 4677311A · Morita · 1987 [cited by examiner]
US 7254742B2 · Hayashi · 2007 [cited by examiner]
US 9104397B2 · Kuroda · 2015 [cited by examiner]
US 20060190747A1 · Fukumori · 2006 [cited by examiner]
US 20110051276A1 · Fukuyama · 2011 [cited by examiner]
US 20110208998A1 · Hosaka · 2011 [cited by examiner]
US 20120159210A1 · Hosaka · 2012 [cited by examiner]
US 20120221801A1 · Okawa · 2012 [cited by examiner]
US 20160004452A1 · Hayes · 2016 [cited by examiner]
US 20160259571A1 · Kumasawa · 2016 [cited by examiner]
US 20160259695A1 · Hosaka · 2016 [cited by examiner]
US 20170344313A1 · Hayasaka · 2017 [cited by examiner]
US 20190332312A1 · Hayashi · 2019 [cited by examiner]
US 20200178337A1 · Hanley · 2020 [cited by examiner]
US 20210271428A1 · Su · 2021 [cited by examiner]
JP 2006235673A · 2006 [cited by applicant]