Half static random access memory (SRAM) cell
An example is a method. A first logical value is written to a latch node of a latch circuit of a half static random access memory (SRAM) cell. A second logical value is read from the latch node. The latch circuit is non-inverter-based. The latch circuit includes a p-type transistor and an n-type transistor. A drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor, and a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor. According to some examples, the half SRAM cell may be implemented as a storage node, for a physical unclonable function (PUF), and/or for data padding.
1 . A method comprising:
writing a first logical value to a latch node of a latch circuit of a half static random access memory (SRAM) cell, the latch circuit being non-inverter-based, the latch circuit including:
a p-type transistor; and
an n-type transistor, wherein:
a drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor as a first node; and
a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor as a second node, the latch circuit being configured to maintain the first node and the second node at logically complementary voltages; and
reading a second logical value from the latch node.
2 . The method of claim 1 , wherein:
the latch node is the first node.
3 . The method of claim 1 , wherein:
the latch node is the second node.
4 . The method of claim 1 , wherein reading the second logical value from the latch node includes:
maintaining a read bit line in node at a high voltage, a first source/drain node of a read access transistor being electrically connected to the read bit line in node, a gate node of the read access transistor being electrically connected to the latch node;
pre-charging a read bit line out node, a second source/drain node of the read access transistor being electrically connected to the read bit line out node;
pulling a voltage of the read bit line in node down to a low voltage; and
capturing a voltage of the read bit line out node as a read value when the voltage of the read bit line in node is pulled down to the low voltage, the read value corresponding to the second logical value.
5 . The method of claim 1 , wherein writing the first logical value to the latch node includes passing the first logical value through a pass gate transistor, wherein:
a first source/drain node of the pass gate transistor is electrically connected to a bit line node;
a second source/drain node of the pass gate transistor is electrically connected to the latch node; and
a gate node of the pass gate transistor is electrically connected to a word line node.
6 . The method of claim 1 , wherein:
writing the first logical value includes writing the first logical value to latch nodes of respective latch circuits of half SRAM cells, each half SRAM cell of the half SRAM cells being an instance of the half SRAM cell; and
reading the second logical value includes reading respective second logical values from the respective latch nodes at a read time after writing the first logical value to the latch nodes, the second logical values each being a function of a random variation of the respective latch circuit and the first logical value, the random variation including process variation.
7 . The method of claim 6 further comprising encrypting data using a cryptography key, the cryptography key being based on the read second logical values.
8 . The method of claim 6 further comprising:
receiving encrypted data; and
decrypting the encrypted data using a cryptography key, the cryptography key being based on the read second logical values.
9 . The method of claim 6 further comprising determining the read time based on a metric of the second logical values, wherein the metric includes a target uniformity, a target uniqueness, or a combination thereof.
10 . The method of claim 1 further comprising obtaining a challenge, the challenge including an indication of a row address of a row of an array of half SRAM cells, each half SRAM cell of the array of half SRAM cells being an instance of the half SRAM cell, wherein:
writing the first logical value includes writing the first logical value to latch nodes of respective latch circuits of half SRAM cells in the row indicated by the row address; and
reading the second logical value includes reading respective second logical values from the respective latch nodes of the respective latch circuits of the half SRAM cells in the row indicated by the row address at a read time after writing the first logical value to the latch nodes, the second logical values each being a function of a random variation of the respective latch circuit and the first logical value, the random variation including process variation, wherein the second logical values are a response to the challenge.
11 . The method of claim 10 further comprising encrypting data using a cryptography key, the cryptography key being based on the response to the challenge.
12 . The method of claim 1 , further comprising:
for each candidate read time of a plurality of candidate read times, determining a metric of respective second logical values for the respective candidate read time, wherein:
for the respective candidate read time:
writing the first logical value includes writing the first logical value to latch nodes of respective latch circuits of half SRAM cells, each half SRAM cell of the half SRAM cells being an instance of the half SRAM cell; and
reading the second logical value includes reading the respective second logical values from the latch nodes at the respective candidate read time after writing the first logical value to the latch nodes; and
determining a read time from the candidate read times based on the respective metrics.
13 . The method of claim 12 , wherein the second logical values are respective functions of process, voltage, and temperature (PVT) variation of the latch circuits and the first logical value.
14 . The method of claim 12 , wherein determining the metric of the second logical values for the respective candidate read time includes determining a uniformity of the second logical values for the respective candidate read time.
15 . The method of claim 12 , wherein determining the metric of the second logical values for the respective candidate read time includes determining a uniqueness of the second logical values for the respective candidate read time.
16 . A non-transitory storage medium storing an electronic representation of a circuit design, the circuit design comprising:
a half static random access memory (SRAM) cell including a latch circuit, the latch circuit being non-inverter-based, the latch circuit including:
a p-type transistor; and
an n-type transistor, wherein:
a drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor as a first node; and
a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor as a second node, the latch circuit being configured to maintain the first node and the second node at logically complementary voltages.
17 . The non-transitory storage medium of claim 16 , wherein the half SRAM cell further includes a first pass gate transistor and a second pass gate transistor, wherein:
a first source/drain node of the first pass gate transistor is electrically connected to a bit line node;
a second source/drain node of the first pass gate transistor is electrically connected to the first node;
a gate node of the first pass gate transistor is electrically connected to a word line node;
a first source/drain node of the second pass gate transistor is electrically connected to a complementary bit line node;
a second source/drain node of the second pass gate transistor is electrically connected to the second node; and
a gate node of the second pass gate transistor is electrically connected to the word line node.
18 . The non-transitory storage medium of claim 16 , wherein the half SRAM cell further includes a read access transistor, wherein:
a first source/drain node of the read access transistor is electrically connected to a read bit line in node;
a second source/drain node of the read access transistor is electrically connected to a read bit line out node; and
a gate node of the read access transistor is electrically connected to the first node.
19 . The non-transitory storage medium of claim 16 , wherein the half SRAM cell further includes a read access transistor, wherein:
a first source/drain node of the read access transistor is electrically connected to a read bit line in node;
a second source/drain node of the read access transistor is electrically connected to a read bit line out node; and
a gate node of the read access transistor is electrically connected to the second node.
20 . A method comprising:
writing a first logical value to a latch node of a latch circuit of a half static random access memory (SRAM) cell, the latch circuit being non-inverter-based, the latch circuit consists of:
a p-type transistor; and
an n-type transistor, wherein:
a source node of the p-type transistor is electrically connected to a first power supply node;
a drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor;
a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor; and
a source node of the n-type transistor is electrically connected to a second power supply node; and
reading a second logical value from the latch node.