IP Library › Granted Patent US 12,393,341
Granted Patent B2
US 12,393,341 · App. 18/463,975 · Granted Aug 19, 2025

Bank to bank data transfer

Inventors: Thanh K. Mai (Allen, TX); Gary L. Howe (Plano, TX); Daniel B. Penney (Wylie, TX)
G06F3/061G06F3/0625G06F3/0646G06F3/0647G06F3/0656G06F3/0659G06F3/0673G06F13/161G11C8/00Y02D10/00
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Quick Facts
Patent No.
US 12,393,341
App. No.
18/463,975
Granted
Aug 19, 2025
Kind
B2
Abstract

The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

Claims (29)

1. An apparatus, comprising:

a processor in memory device (PIM) comprising a plurality of banks of memory cells, each bank of memory cells of the plurality of banks of memory cells is in communication with a respective sense amplifier and compute component, wherein the PIM receives one or more commands including instructions to transfer data between the plurality banks, and the PIM is configured to:

transfer the data between the plurality of banks of memory cells, via at least the respective compute components, by executing the one of more commands, wherein the one or more commands include source bank information used to identify a source bank to read the data from and destination bank information used to identify a destination bank to write the data to.

2. The apparatus of claim 1 , wherein the data transferred between the plurality of banks includes program instructions for the PIM device to perform operations on data stored in the plurality of banks.

3. The apparatus of claim 1 , wherein the source bank is identified by a first number of bits and the destination bank is identified by a second number of bits.

4. The apparatus of claim 1 , wherein, to transfer the data between the plurality of banks of memory cells, the PIM device is configured to perform a read command that transfers the data from the plurality of banks to a number of buffers isolated from a number of DQs.

5. The apparatus of claim 1 , wherein the PIM device is coupled to a host via a bus.

6. The apparatus of claim 5 , wherein the host is configured to send another command to the PIM device to perform an operation using the data transferred between the plurality of banks.

7. The apparatus of claim 1 , wherein the PIM device is configured to cause the transfer of the data on an internal data bus that couples the plurality of banks of memory cells together and wherein the internal data bus is coupled to an external data bus that is configured to transfer the data between the plurality of banks of memory cells and a host.

8. The apparatus of claim 7 , wherein the internal data bus that couples the plurality of banks of memory cells together is coupled to a number of DQs to transfer the data from the plurality of banks of memory cells.

9. A system, comprising:

a host configured to provide instructions for transferring data; and

a processor in memory (PIM) device, coupled to the host, comprising:

a plurality of banks of memory cells, wherein each bank of the plurality of banks is in communication with a respective sense amplifier and a respective compute component, and wherein the PIM device, via the respective compute components, is configure to:

transfer the data between the plurality of banks of memory cells by:

performing a number of read commands that transfer the data from the plurality of banks to a number of buffers and a number of write commands that transfer the data from the number of buffers to the plurality of banks, wherein source bank information is used to identify a source bank to read the data from and destination bank information is used to identify a destination bank to write the data to.

10. The system of claim 9 , wherein the PIM device is configured to perform an operation on data stored in the plurality of banks using program instructions in the data transferred between the plurality of banks according to the instructions from the host.

11. The system of claim 10 , wherein a result of the operation is transferred from the PIM device to the host.

12. The system of claim 10 , wherein the host includes a channel controller configured to send a command to the PIM device to perform the operation.

13. A method of operating a processor in memory (PIM) device, comprising:

receiving one or more commands to transfer data between a plurality of banks of the PIM device, wherein each bank of the plurality of banks is in communication with a respective sense amplifier and a respective compute component; and

transferring the data from a first bank of memory cells in the PIM device to a second bank of memory cells in the PIM device via a first compute component in communication with the first bank of memory cells and a second compute component in communication with the second bank of memory cells by executing the one or more commands, wherein the one or more commands include source bank information identifying a source bank to read the data from and destination bank information identifying a destination bank to write the data to.

14. The method of claim 13 , wherein transferring the data from the first bank to the second bank stores program instructions for performing an operation on the PIM device using one of the respective compute components of the PIM device.

15. The method of claim 14 , further including performing the operation on the PIM device using the program instructions stored on the second bank.

16. The method of claim 13 , wherein transferring the data from the first bank to the second bank includes transferring the data on an internal data bus without transferring the data on an external data bus.

17. The method of claim 13 , wherein the method further comprises performing a silent read command to transfer the data from the first bank to a number of buffers isolated from a number of DQs on an internal data bus.

18. The method of claim 17 , wherein the method further comprises performing a write command to transfer the data from the number of buffers isolated from the number of DQs on the internal data bus to the second bank.

19. The method of claim 13 , wherein transferring the data from the first bank of memory cells to the second bank of memory cells comprises performing a bank to bank data transfer command that identifies, simultaneously, the first bank as the source bank and the second bank as the destination bank.

20. The method of claim 13 , wherein transferring the data from the first bank of memory cells in the PIM device to the second bank of memory cells in the PIM device includes enabling bidirectional buffers for transferring the data on an internal data path based on the source bank information and the destination bank information.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 067872/0861 →
Continuity (4)
Continuation 17178889 · Feb 18, 2021
Continuation 16541764 · Aug 15, 2019
Continuation 15189900 · Jun 22, 2016
Related Publication 20240176487A1 · May 30, 2024
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