Co-manufacturing of silicon-on-insulator waveguides and silicon nitride waveguides for hybrid photonic integrated circuits
A method of co-manufacturing silicon waveguides, SiN waveguides, and semiconductor structures in a photonic integrated circuit. A silicon waveguide structure can be formed using a suitable process, after which it is buried in a cladding. The cladding is polished, and a silicon nitride layer is disposed to define a silicon nitride waveguide. The silicon nitride waveguide is buried in a cladding, and annealed. Thereafter, cladding above the silicon waveguide structure can be trenched through, and low-temperature operations can be performed to or with an exposed surface of the silicon waveguide structure.
1. A method of manufacturing a hybrid photonic integrated circuit, the method comprising:
forming a silicon structure over a base substrate;
burying the silicon structure in a first dielectric layer;
forming a silicon nitride structure over the first dielectric layer;
burying the silicon nitride structure in a second dielectric layer;
trenching through at least the first dielectric layer to expose a surface of the silicon structure;
implanting the surface with an implant and activating the implant;
disposing a third dielectric layer over the surface;
defining a via through the third dielectric layer; and
conductively coupling through the via to the surface of the silicon structure.
2. The method of claim 1 , wherein the silicon structure comprises a silicon waveguide.
3. The method of claim 1 , wherein the silicon nitride structure comprise a silicon nitride waveguide.
4. The method of claim 1 , comprising:
annealing the first dielectric layer; and
after annealing the first dielectric layer, polishing the first dielectric layer.
5. The method of claim 4 , comprising:
annealing the silicon nitride structure; and
after annealing the silicon nitride structure, burying the silicon nitride structure in the second dielectric layer.
6. The method of claim 5 , comprising annealing the second dielectric layer prior to trenching.
7. The method of claim 1 , comprising forming a metal layer over the third dielectric layer, the metal layer defining an electrical contact conductively coupled to the surface of the silicon structure through the via.
8. The method of claim 1 , wherein trenching through at least the first dielectric layer comprises chemically etching the first dielectric layer above the surface of the silicon structure.
9. The method of claim 1 , comprising trenching through both the first dielectric layer and the second dielectric layer to expose the surface of the silicon structure.
10. The method of claim 1 , wherein the surface of the silicon structure is a portion of a thermo-optic heater element.
11. The method of claim 1 , wherein the silicon nitride structure is positioned over and at least partially aligned with the silicon structure that light confined by a first waveguide defined by the silicon nitride structure can couple into a second waveguide defined by the silicon structure.
12. The method of claim 11 , wherein the first waveguide is separated from the second waveguide by the first dielectric layer.
13. A method of manufacturing a hybrid photonic integrated circuit, the method comprising:
defining a silicon structure on an insulator layer;
burying the silicon structure in a first dielectric layer;
annealing the first dielectric layer;
forming a silicon nitride layer on the first dielectric layer;
burying the silicon nitride layer in a second dielectric layer;
annealing the second dielectric layer;
disposing a lithographic mask over a silicon waveguide and a silicon nitride waveguide;
selectively etching the annealed first and second dielectric layers to expose a portion of the silicon nitride layer;
removing the portion of the silicon nitride layer;
trenching through a portion of the first dielectric layer below the portion of the silicon nitride layer to expose a surface of the silicon structure; and
performing a temperature-sensitive operation with the surface of the silicon structure.
14. The method of claim 13 , comprising annealing the silicon nitride layer prior to burying the silicon nitride layer in the second dielectric layer.
15. The method of claim 13 , wherein the silicon waveguide and the silicon nitride waveguide define an optical transition and are separated by an interlayer gap.
16. The method of claim 13 , wherein the temperature-sensitive operation comprises disposing a metal contact over at least a portion of the surface of the silicon structure.
17. A method of manufacturing a photonic circuit, the method comprising:
forming a first semiconductor layer using a first high temperature process;
burying the first semiconductor layer in a first dielectric layer;
forming a second semiconductor layer using a second high temperature process;
burying the second semiconductor layer in a second dielectric layer having a thickness that exceeds the first dielectric layer;
etching through a portion of the second dielectric layer over the first semiconductor layer, using the second semiconductor layer as an etch stop, exposing a surface of the first dielectric layer;
etching through the surface of the first dielectric layer to expose a portion of the first semiconductor layer;
implanting and activating an implant within the portion of the first semiconductor layer in a low temperature process; and
conductively coupling the implant to a circuit.
18. The method of claim 17 , wherein the first semiconductor layer defines an optical waveguide.
19. The method of claim 17 , wherein the second semiconductor layer defines an optical waveguide.
20. The method of claim 17 , wherein at least one of the first high temperature process or the second high temperature process comprising annealing a layer of the photonic circuit.