Granted Patent B2

US 12,369,302 · App. 18/469,971 · Granted Jul 22, 2025

Inventors: Koji Sakui (Tokyo, JP); Nozomu Harada (Tokyo, JP)

Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

H10B12/20G11C11/404G11C11/4087G11C11/4091G11C11/4096

Abstract

Claims (32)

1. A memory device using a semiconductor element, the memory device including at least one bank, the bank including a plurality of pages arranged in a column direction on a substrate in plan view, each of the plurality of pages including a plurality of memory cells arranged in a row direction, wherein each of the memory cells included in each of the pages comprises:

a semiconductor base standing vertically or extending horizontally on the substrate;

a first impurity region and a second impurity region at both ends of the semiconductor base;

a gate insulating layer in contact with a side surface of the semiconductor base between the first impurity region and the second impurity region;

a first gate conductor layer covering a part or an entirety of the gate insulating layer; and

a second gate conductor layer adjacent to the first gate conductor layer and in contact with a side surface of the gate insulating layer;

in each of the memory cells, the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and an other of the first gate conductor layer and the second gate conductor layer is connected to a plate line;

a page erase operation, a page write operation, and a page read operation are to be performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line;

the bit line is connected to a sense amplifier circuit with a switch circuit interposed therebetween, the sense amplifier circuit is connected to a column decoder circuit, a column address is to be input to the column decoder circuit, and the sense amplifier circuit is to be selectively connected to an input/output circuit in accordance with the column address; and

among a first page and a second page included in the same bank, a first operation in which data of the first page is output to the input/output circuit via the sense amplifier circuit and a second operation in which data of the second page is read to the bit line are to be performed in parallel.

2. The memory device using the semiconductor element according to claim 1 , wherein

in the page erase operation to be performed by controlling the voltages applied to the source line, the bit line, the word line, and the plate line, some of a group of positive holes in the semiconductor base of the memory cells of the page are eliminated to reduce a number of positive holes remaining in the semiconductor base, and

in the page write operation to be performed by controlling the voltages applied to the source line, the bit line, the word line, and the plate line, the number of positive holes remaining in the semiconductor base of a selected memory cell among the memory cells of the page is increased by an impact ionization phenomenon.

3. The memory device using the semiconductor element according to claim 1 , wherein

the word line and the plate line are arranged in parallel in plan view, and

the bit line is arranged in a direction perpendicular to the word line and the plate line in plan view.

4. The memory device using the semiconductor element according to claim 1 , wherein

a first gate capacitance between the semiconductor base and the other of the first gate conductor layer and the second gate conductor layer, to which the plate line is connected, is larger than a second gate capacitance between the semiconductor base and the one of the first gate conductor layer and the second gate conductor layer, to which the word line is connected.

5. The memory device using the semiconductor element according to claim 1 , wherein

the source line is isolated for each of the memory cells arranged in the row direction and is arranged in parallel with the word line and the plate line in plan view.

6. The memory device using the semiconductor element according to claim 1 , wherein

the source line is connected in common to all the memory cells of adjacent pages among the pages in plan view.

7. The memory device using the semiconductor element according to claim 1 , wherein

the semiconductor base is a P-type semiconductor layer, and the first impurity region and the second impurity region are N-type semiconductor layers.

8. The memory device using the semiconductor element according to claim 1 , wherein

data in all the memory cells connected to at least two pages among the pages is erased in the page erase operation.

9. The memory device using the semiconductor element according to claim 1 , wherein

the word line and the plate line are connected to a row decoder circuit, a row address is to be input to the row decoder circuit, and any page among the pages is to be selected in accordance with the row address.

10. The memory device using the semiconductor element according to claim 1 , wherein

one or both of the first gate conductor layer and the second gate conductor layer are divided into two or more isolated gate conductor layers in plan view or in a vertical direction, and the isolated gate conductor layers are to be operated synchronously or asynchronously.

11. The memory device using the semiconductor element according to claim 10 , wherein

in plan view or in the vertical direction, the isolated gate conductor layers of one of the first gate conductor layer and the second gate conductor layer are arranged on both sides of an other of the first gate conductor layer and the second gate conductor layer.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (24)