Method and apparatus for translating memory addresses in manycore system

1. A method for translating memory addresses in a manycore system, the method being executed by one or more processors and comprising:

after a thread associated with one or more tasks according to an offloading request from a host processor is created and assigned to one or more cores of a cluster that includes a plurality of cores, receiving, by a memory access module of the one or more cores, translation setting information for determining a physical address of data in a memory associated with the one or more cores accessed by the thread;

receiving, by the memory access module, identification information of the thread accessing the memory;

receiving, by the memory access module, a virtual address of data accessed by the thread; and

determining, by the memory access module, a physical address of the data in the memory based on the translation setting information, the virtual address, and the identification information of the thread,

wherein the method is performed by the core without intervention of an operating system of the manycore system.

2. The method according to claim 1 , wherein the determining the physical address of the data includes:

determining a start address of a segment where the data is included based on the virtual address;

calculating an address correction value associated with the thread based on the identification information of the thread; and

determining an address obtained by adding the address correction value to the start address of the segment as the physical address of the data.

3. The method according to claim 2 , wherein the determining the start address of the segment includes determining the start address of the segment based on the virtual address and a value of a register associated with the segment where the data is included.

4. The method according to claim 2 , wherein a size of the segment is determined based on user input.

5. The method according to claim 2 , wherein a size of the segment is determined based on a size of a data structure of the data.

6. The method according to claim 2 , wherein the calculating the address correction value associated with the thread includes calculating the address correction value by performing a shift-left operation on a value of the identification information of the thread based on a size of the segment.

7. The method according to claim 1 , wherein the translation setting information includes information on a size of an area of the virtual address and a starting point of the area, and

the determining the physical address of the data includes determining a physical address of the data based on the size of the area of the virtual address, information on the starting point of the area, and the identification information of the thread.

8. A non-transitory computer-readable recording medium storing instructions for execution by the one or more processors that, when executed by the one or more processors, cause the one or more processors to perform the method according to claim 1 .

9. A manycore system comprising:

one or more clusters comprising a plurality of cores; and

a memory access module that controls access to a memory associated with one or more cores of the one or more clusters,

wherein the memory access module is configured to:

after a thread associated with one or more tasks according to an offloading request from a host processor is created and allocated to the one or more cores, receive translation setting information for determining a physical address of data in a memory associated with the one or more cores accessed by the thread;

receive the identification information of the thread accessing the memory;

receive a virtual address of data accessed by the thread; and

determine a physical address of the data in the memory based on the translation setting information, the virtual address, and the identification information of the thread, and

the determining is performed by the memory access module without intervention of an operating system of the manycore system.