Apparatus and method for supporting synchronization of reconfigurable intelligent surface (RIS) reflection pattern in wireless communication system
The present disclosure relates to a fifth generation (5G) communication system or a sixth generation (6G) communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). In a wireless communication system, a method performed by a base station includes identifying a delay time caused by a radio unit (RU) buffer, determining an RIS offset value for synchronization of signals transmitted to a reconfigurable intelligent surface (RIS), based on the delay time caused by the RU buffer, transmitting, to the RIS, a first signal to be transmitted to a terminal through a reflection plane of the RIS at a first time point, and transmitting, to the RIS, a second signal for controlling a reflection pattern of the RIS at a second time point to which the RIS offset value is applied.
1 . A method performed by a base station in a wireless communication system, the method comprising:
identifying a delay time caused by a radio unit (RU) buffer;
determining a reconfigurable intelligent surface (RIS) offset value for synchronization of signals transmitted to an RIS, based on the delay time caused by the RU buffer;
transmitting, to the RIS, a first signal to be transmitted to a terminal through a reflection plane of the RIS at a first time point; and
transmitting, to the RIS, a second signal for controlling a reflection pattern of the RIS at a second time point to which the RIS offset value is applied.
2 . The method of claim 1 ,
wherein the second time point to which the RIS offset value is applied comprises a time point after the RIS offset value from the first time point.
3 . The method of claim 1 , further comprising, in case that the RIS offset value is not applied to the second time point at which the second signal is transmitted, transmitting the second signal for controlling the reflection pattern of the RIS to the RIS at the first time point,
wherein the second signal comprises information indicating to control the reflection pattern of the RIS after the RIS offset value from the time point at which the RIS receives the control signal.
4 . The method of claim 1 , further comprising:
determining a slot for switching the RIS reflection pattern; and
transmitting the first signal including the determined slot for switching the RIS reflection pattern to the RIS.
5 . The method of claim 4 ,
wherein the slot for switching the RIS reflection pattern is determined based on an error value of the delay time caused by the buffer in case that the error value of the delay time caused by the buffer exists.
6 . The method of claim 4 ,
wherein the slot for switching the RIS reflection pattern is determined based on a first delay time indicating a maximum value of a size of the buffer and a second delay time indicating a minimum value of a size of the buffer.
7 . The method of claim 1 , further comprising identifying a delay time caused by switching of the reflection pattern of the RIS,
wherein the RIS offset value is determined based on the identified delay time caused by switching the reflection pattern of the RIS, and
wherein the second time point to which the RIS offset value is applied comprises a time point before the RIS offset value from the first time point.
8 . The method of claim 7 , further comprising:
identifying RSI control information (RCI) for the RIS reflection pattern corresponding to the first signal; and
transmitting the first signal including the RCI to the RIS at the first time point.
9 . The method of claim 8 ,
wherein the RCI is included in the first signal based on at least one of a Zadoff-Chu sequence, a computer-generated (CG) sequence, or a pseudo-random noise (PN) sequence by a correlation-based detection.
10 . The method of claim 1 ,
wherein the RIS offset value is determined based on at least one of a distance between the RU antenna and the reflection plane of the RIS and a voltage change of a pin diode connected to the reflection plane of the RIS.
11 . A base station in a wireless communication system, the base station comprising:
a transceiver; and
a controller coupled with the transceiver, and configured to:
identify a delay time caused by a radio unit (RU) buffer,
determine a reconfigurable intelligent surface (RIS) offset value for synchronization of signals transmitted to an RIS, based on the delay time caused by the RU buffer,
transmit, to the RIS, a first signal to be transmitted to a terminal through a reflection plane of the RIS at a first time point, and
transmit, to the RIS, a second signal for controlling a reflection pattern of the RIS at a second time point to which the RIS offset value is applied.
12 . The base station of claim 11 ,
wherein the second time point to which the RIS offset value is applied comprises a time point after the RIS offset value from the first time point.
13 . The base station of claim 11 ,
wherein, in case that the RIS offset value is not applied to the second time point at which the second signal is transmitted, the at least one processor is further configured to transmit the second signal for controlling the reflection pattern of the RIS to the RIS at the first time point, and
wherein the second signal comprises information indicating to control the reflection pattern of the RIS after the RIS offset value from the time point at which the RIS receives the control signal.
14 . The base station of claim 11 , wherein the controller is further configured to:
determine a slot for switching the RIS reflection pattern; and
transmit the first signal including the determined slot for switching the RIS reflection pattern to the RIS.
15 . The base station of claim 14 ,
wherein the slot for switching the RIS reflection pattern is determined based on an error value of the delay time caused by the buffer in case that the error value of the delay time caused by the buffer exists.
16 . The base station of claim 14 ,
wherein the slot for switching the RIS reflection pattern is determined based on a first delay time indicating a maximum value of a size of the buffer and a second delay time indicating a minimum value of a size of the buffer.
17 . The base station of claim 11 , wherein the controller is further configured to identify a delay time caused by switching the reflection pattern of the RIS,
wherein the RIS offset value is determined based on the identified delay time caused by switching the reflection pattern of the RIS, and
wherein the second time point to which the RIS offset value is applied comprises a time point before the RIS offset value from the first time point.
18 . The base station of claim 17 , wherein the controller is further configured to:
identify RSI control information (RCI) for the RIS reflection pattern corresponding to the first signal; and
transmit the first signal including the RCI to the RIS at the first time point.
19 . The base station of claim 18 ,
wherein the RCI is included in the first signal based on at least one of a Zadoff-Chu sequence, a computer-generated (CG) sequence, or a pseudo-random noise (PN) sequence by a correlation-based detection.
20 . The base station of claim 11 ,
wherein the RIS offset value is determined based on at least one of a distance between the RU antenna and the reflection plane of the RIS and a voltage change of a pin diode connected to the reflection plane of the RIS.