METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A TRENCH CAPACITOR AND A LOGIC DEVICE

1 . A method of manufacturing a semiconductor device, the method comprising:

forming a deep trench in a substrate;

performing an ion implantation process to form a lower electrode along with the deep trench;

forming a dielectric layer on the lower electrode;

filling a first conductive layer into the deep trench;

performing a planarization process on the first conductive layer to form an upper electrode in the deep trench such that a trench capacitor is formed in the deep trench;

forming a shallow trench adjacent to the deep trench;

forming a logic gate insulating layer adjacent to the shallow trench;

forming a logic gate electrode on the logic gate insulating layer; and

forming a source region and a drain region adjacent to the logic gate electrode,

wherein the logic gate electrode is made of a same material as the upper electrode.

2 . The method of claim 1 , wherein the forming of the deep trench in the substrate comprises:

forming a deep trench hard mask pattern on the substrate; and

performing an etching process on the substrate to form the deep trench with the deep trench hard mask pattern.

3 . The method of claim 1 , wherein the forming of the dielectric layer on the lower electrode comprises:

forming a first dielectric layer in the deep trench; and

forming a second dielectric layer on the first dielectric layer, and

wherein the first dielectric layer comprises a first material that is different from a second material of the second dielectric layer.

4 . The method of claim 1 , further comprising:

forming thermal oxide layers on the upper electrode and the logic gate electrode; and

forming spacers on sidewalls of the upper electrode and the logic gate electrode.

5 . The method of claim 1 , further comprising:

performing a high temperature annealing process on the planarized first conductive layer or the upper electrode.

6 . The method of claim 1 , wherein the performing of the planarization process on the first conductive layer to form the upper electrode in the deep trench comprises:

performing a first chemical mechanical planarization (CMP) process on the first conductive layer to form a planarized first conductive layer; and

performing a second CMP process to remove the dielectric layer exposed by the first CMP.

7 . The method of claim 1 , further comprising:

performing a gap-fill process on the shallow trench with a thick insulating layer; and

performing a third CMP process on the thick insulating layer.

8 . A method of manufacturing a semiconductor device, the method comprising:

providing a first region and a second region in a semiconductor substrate;

forming a deep trench hard mask pattern in the second region;

forming a deep trench in the second region with the deep trench hard mask pattern;

forming a lower electrode along with the deep trench;

forming a dielectric layer on the lower electrode;

performing a gap-filling process in the deep trench with a first conductive layer;

performing a first planarization process on the first conductive layer to form an upper electrode in the deep trench;

forming a shallow trench hard mask pattern in the first region;

forming a shallow trench in the first region with the shallow trench hard mask pattern;

filling the shallow trench with a thick insulating layer;

performing a second planarization process on the thick insulating layer to form a planarized thick insulating layer in the shallow trench;

forming a logic gate insulating layer adjacent to the shallow trench;

forming a second conductive layer on the logic gate insulating layer;

performing a patterning process on the second conductive layer to form a logic gate electrode in the first region; and

forming a source region and a drain region around the logic gate electrode, wherein the first conductive layer is a same material as the second conductive layer.

9 . The method of claim 8 , wherein the forming of the lower electrode comprises performing an ion implantation process along with the deep trench.

10 . The method of claim 8 , further comprising:

forming a thermal oxide layer on each surface of the logic gate electrode and the upper electrode.

11 . The method of claim 8 , wherein the performing of the first planarization process on the first conductive layer to form the upper electrode in the deep trench comprises:

performing a first chemical mechanical planarization (CMP) process on the first conductive layer to form a planarized first conductive layer; and performing a second CMP process to remove the dielectric layer exposed by the first CMP.

12 . The method of claim 8 , further comprising:

performing a high temperature annealing process on the planarized first conductive layer or the upper electrode.

13 . A method of manufacturing a semiconductor device, the method comprising:

providing a first region and a second region in a substrate;

forming a deep trench in the second region;

forming a lower electrode along with the deep trench;

forming a dielectric layer on the lower electrode;

filling a first conductive layer into the deep trench;

performing a planarization process on the first conductive layer to form an upper electrode in the deep trench such that a trench capacitor is formed in the deep trench;

forming a shallow trench adjacent to the deep trench;

filling the shallow trench with a thick insulating layer to form a shallow trench isolation;

forming a first gate insulating layer on the substrate in the first region, and forming a second gate insulating layer on the upper electrode in the second region;

forming a second conductive layer on the first and second gate insulating layers;

performing a patterning process on the second conductive layer to form a logic gate electrode in the first region; and

forming source and drain regions adjacent to the logic gate electrode.

14 . The method of claim 13 , wherein the dielectric layer comprises a first insulating layer, a second insulating layer, and a third insulating layer, and

wherein the first and third insulating layers are formed of a same material, and the second insulating layer is formed of a material different from that of the first and third insulating layers.

15 . The method of claim 14 , wherein the first and third insulating layers comprise Al 2 O 2 or SiO 2 , and the second insulating layer comprises HfO 2 , SiN or SiON.