Granted Patent B2

US 12,751,050 · App. 18/479,428 · Granted Sep 29, 2026

Inventors: Jeeeun Yang (Suwon-si, KR); Sangwook Kim (Suwon-si, KR); Euntae Kim (Suwon-si, KR); Kwanghee Lee (Suwon-si, KR); Moonil Jung (Suwon-si, KR)

Assignee: Samsung Electronics Co., Ltd.

H10D30/6755H10D30/031H10D30/673

Abstract

Claims (61)

1 . A semiconductor device comprising:

a substrate;

a lower electrode on the substrate;

a first buffer layer on the lower electrode, the first buffer layer including first indium;

an oxide semiconductor layer on the first buffer layer, the oxide semiconductor layer including second indium;

a gate insulating layer on the oxide semiconductor layer;

a gate electrode on the gate insulating layer; and

an upper electrode on the oxide semiconductor layer,

wherein a content of the first indium in the first buffer layer is greater than a content of the second indium in the oxide semiconductor layer,

wherein the first buffer layer is between the lower electrode and the oxide semiconductor layer,

wherein the upper electrode and the lower electrode are spaced apart from each other in a perpendicular direction extending perpendicular to the substrate,

wherein the oxide semiconductor layer includes a first area and a second area,

wherein a distance from the first area of the oxide semiconductor layer to the first buffer layer is smaller than a distance from the second area of the oxide semiconductor layer to the first buffer layer, and

wherein a content of the second indium in the first area of the oxide semiconductor layer is greater than a content of the second indium in the second area of the oxide semiconductor layer.

2 . The semiconductor device of claim 1 , wherein the first buffer layer is in contact with each of the lower electrode and the oxide semiconductor layer.

3 . The semiconductor device of claim 1 , wherein the first buffer layer comprises at least one of InGaZnO, InGaO, InSnO, InZnO, and InO.

4 . The semiconductor device of claim 1 , wherein the lower electrode includes Zn having a content of 10 at % or less.

5 . The semiconductor device of claim 1 , wherein Zn content in the first buffer layer is less than In content in the first buffer layer.

6 . The semiconductor device of claim 1 , wherein the first buffer layer has a thickness in a range from about 1 Å to about 50 Å.

7 . The semiconductor device of claim 1 , wherein the oxide semiconductor layer comprises an oxide comprising at least one of Zn, Sn, Ga, and Hf.

8 . The semiconductor device of claim 1 , further comprising a metal oxide layer between the lower electrode and the first buffer layer,

wherein the metal oxide layer comprises a same metal as a metal included in the lower electrode.

9 . The semiconductor device of claim 1 , wherein the oxide semiconductor layer comprises InGaZnO, ZrInZnO, InGaZnO 4 , ZnInO, In 2 O 3 , HfInZnO, or any combination thereof.

10 . The semiconductor device of claim 1 , wherein the oxide semiconductor layer comprises the second indium and zinc (Zn), and the content of the second indium in the oxide semiconductor layer is greater than or equal to a content of Zn in the oxide semiconductor layer.

11 . The semiconductor device of claim 1 , wherein the lower electrode comprises at least one of tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), tin (Sn), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), or magnesium (Mg).

12 . The semiconductor device of claim 1 , wherein the gate electrode surrounds a circumference of the oxide semiconductor layer.

13 . The semiconductor device of claim 1 , further comprising a second buffer layer between the oxide semiconductor layer and the upper electrode.

14 . The semiconductor device of claim 1 , wherein

the first buffer layer is in contact with a side surface of the lower electrode, and

at least a portion of the oxide semiconductor layer is offset from the lower electrode and the upper electrode in a horizontal direction that extends parallel with the substrate, and the portion of the oxide semiconductor layer extends in the perpendicular direction between at least a first position that overlaps the lower electrode in the horizontal direction and a second position that overlaps the upper electrode in the horizontal direction.

15 . The semiconductor device of claim 1 , wherein the oxide semiconductor layer, the gate insulating layer, and the gate electrode are arranged such that

the oxide semiconductor layer, the gate insulating layer, and the gate electrode have respective length directions that are parallel with each other and parallel to the perpendicular direction, and

the oxide semiconductor layer, the gate insulating layer, and the gate electrode are arranged in a horizontal direction extending parallel with the substrate such that the oxide semiconductor layer, the gate insulating layer, and the gate electrode at least partially overlap with each other in the horizontal direction.

16 . The semiconductor device of claim 1 , wherein the oxide semiconductor layer has a U-shaped cross-section.

17 . The semiconductor device of claim 1 , wherein

the oxide semiconductor layer comprises

a first oxide semiconductor layer that has an L-shape having a length dimension and a width dimension extending perpendicular to each other such that the length dimension of the first oxide semiconductor layer extends in the perpendicular direction, and

a second oxide semiconductor layer that is symmetrically arranged with respect to the first oxide semiconductor layer with respect to the perpendicular direction such that the first oxide semiconductor layer and the second oxide semiconductor layer have reflection symmetry around a first axis of symmetry that extends in the perpendicular direction, and the gate electrode comprises

a first gate electrode having a length dimension that extends in the perpendicular direction, and

a second gate electrode that is symmetrically arranged with respect to the first gate electrode with respect to the perpendicular direction such that the first gate electrode and the second gate electrode have reflection symmetry around a second axis of symmetry that extends in the perpendicular direction.

18 . The semiconductor device of claim 1 , wherein the lower electrode, the first buffer layer, and the oxide semiconductor layer have a same width as each other.

19 . A method of manufacturing a semiconductor device, the method comprising:

arranging a lower electrode on a substrate;

depositing, on the lower electrode, a buffer layer including first indium;

depositing, on the buffer layer, an oxide semiconductor layer including second indium;

depositing a gate insulating layer on the oxide semiconductor layer;

depositing a gate electrode on the gate insulating layer; and

depositing an upper electrode on the oxide semiconductor layer,

wherein a content of the first indium in the buffer layer is greater than a content of the second indium in the oxide semiconductor layer,

wherein the buffer layer is between the lower electrode and the oxide semiconductor layer,

wherein the upper electrode and the lower electrode are spaced apart from each other in a perpendicular direction that extends perpendicular to the substrate,

wherein the oxide semiconductor layer includes a first area and a second area,

wherein a distance from the first area of the oxide semiconductor layer to the buffer layer is smaller than a distance from the second area of the oxide semiconductor layer to the buffer layer, and

wherein a content of the second indium in the first area of the oxide semiconductor layer is greater than a content of the second indium in the second area of the oxide semiconductor layer.

20 . The method of claim 19 , wherein the buffer layer is in contact with each of the lower electrode and the oxide semiconductor layer.

21 . The method of claim 19 , wherein the buffer layer comprises at least one of InGaZnO, InGaO, InSnO, InZnO, and InO.

22 . The method of claim 19 , wherein the buffer layer has a thickness in a range from about 1 Å to about 50 Å.

23 . The method of claim 19 , wherein the depositing of the buffer layer on the lower electrode comprises an atomic layer deposition (ALD) process.

24 . The method of claim 19 , wherein the depositing of the oxide semiconductor layer comprises an atomic layer deposition (ALD) process.

25 . The method of claim 19 , wherein the lower electrode comprises Zn having a content of 10 at % or less.

26 . The method of claim 19 , wherein Zn content in the buffer layer is less than In content in the buffer layer.

Assignments (1)

Priority Claims (2)

Continuity (1)

References Cited (34)