System and method of clock and data recovery
A system and method of clock and data recovery. In some embodiments, the method includes: setting a bias signal source to a first bias value, the bias signal source being connected to an input of a voltage-controlled oscillator of a clock and data recovery circuit; determining that a locked signal of a frequency feedback signal source equals a first feedback value; setting the bias signal source to a second bias value, different from the first bias value; determining that a locked signal of the frequency feedback signal source equals a second feedback value; determining that the second feedback value meets a termination criterion; and setting an operating value of the bias signal source to the second bias value.
1 . A method, comprising:
setting a bias signal source to a first bias value, the bias signal source being connected to an input of a voltage-controlled oscillator of a clock and data recovery circuit;
determining that a locked signal of a frequency feedback signal source equals or exceeds a first feedback value;
determining that the first feedback value does not meet a termination criterion;
setting the bias signal source to a second bias value, different from the first bias value;
determining that the locked signal of the frequency feedback signal source equals or exceeds a second feedback value;
determining that the second feedback value meets the termination criterion; and
based on determining that the second feedback value meets the termination criterion, setting an operating value of the bias signal source to the second bias value for the voltage-controlled oscillator of the clock and data recovery circuit.
2 . The method of claim 1 , wherein the determining that the second feedback value meets the termination criterion comprises determining that a difference between the second feedback value and a target value is less than a threshold.
3 . The method of claim 2 , wherein the frequency feedback signal source comprises a digital to analog converter.
4 . The method of claim 3 , wherein the locked signal of the frequency feedback signal source is an input value of the digital to analog converter.
5 . The method of claim 3 , wherein the locked signal of the frequency feedback signal source is an output value of the digital to analog converter.
6 . The method of claim 1 , wherein the determining that the second feedback value meets the termination criterion comprises determining that a difference between the second feedback value and a target value is less than the difference between the first feedback value and the target value.
7 . The method of claim 6 , wherein the frequency feedback signal source comprises a digital to analog converter.
8 . The method of claim 7 , wherein the locked signal of the frequency feedback signal source is an input value of the digital to analog converter.
9 . The method of claim 7 , wherein the locked signal of the frequency feedback signal source is an output value of the digital to analog converter.
10 . A system, comprising:
a clock and data recovery circuit comprising:
a voltage-controlled oscillator;
a bias signal source connected to a first input of the voltage-controlled oscillator;
a frequency feedback signal source connected to a second input of the voltage-controlled oscillator; and
a processing circuit configured to perform a method,
the method comprising:
setting the bias signal source to a first bias value;
determining that a locked signal of the frequency feedback signal source equals or exceeds a first feedback value;
determining that the first feedback value does not meet a termination criterion;
setting the bias signal source to a second bias value, different from the first bias value;
determining that the locked signal of the frequency feedback signal source equals or exceeds a second feedback value;
determining that the second feedback value meets the termination criterion; and
based on determining that the second feedback value meets the termination criterion, setting an operating value of the bias signal source to the second bias value for the voltage-controlled oscillator of the clock and data recovery circuit.
11 . The system of claim 10 , wherein the determining that the second feedback value meets the termination criterion comprises determining that a difference between the second feedback value and a target value is less than a threshold.
12 . The system of claim 11 , wherein the frequency feedback signal source comprises a digital to analog converter.
13 . The system of claim 12 , wherein the locked signal of the frequency feedback signal source is an input value of the digital to analog converter.
14 . The system of claim 12 , wherein the locked signal of the frequency feedback signal source is an output value of the digital to analog converter.
15 . The system of claim 10 , wherein the determining that the second feedback value meets the termination criterion comprises determining that a difference between the second feedback value and a target value is less than the difference between the first feedback value and the target value.
16 . The system of claim 15 , wherein the frequency feedback signal source comprises a digital to analog converter.
17 . The system of claim 16 , wherein the locked signal of the frequency feedback signal source is an input value of the digital to analog converter.
18 . The system of claim 16 , wherein the locked signal of the frequency feedback signal source is an output value of the digital to analog converter.
19 . The system of claim 10 , wherein the processing circuit is a finite state machine.
20 . A system, comprising:
a clock and data recovery circuit comprising:
a voltage-controlled oscillator;
a bias signal source connected to a first input of the voltage-controlled oscillator;
a frequency feedback signal source connected to a second input of the voltage-controlled oscillator; and
means for processing configured to perform a method,
the method comprising:
setting the bias signal source to a first bias value;
determining that a locked signal of the frequency feedback signal source equals or exceeds a first feedback value;
determining that the first feedback value does not meet a termination criterion;
setting the bias signal source to a second bias value, different from the first bias value;
determining that the locked signal of the frequency feedback signal source equals or exceeds a second feedback value;
determining that the second feedback value meets the termination criterion; and
based on determining that the second feedback value meets the termination criterion, setting an operating value of the bias signal source to the second bias value for the voltage-controlled oscillator of the clock and data recovery circuit.