IP Library › Granted Patent US 12,601,873
Granted Patent B2
US 12,601,873 · App. 18/481,526 · Granted Apr 14, 2026

Optical connection structure and optical module

Inventor: Kazuhiro Yoshida (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
G02B6/1228G02B2006/12061
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Quick Facts
Patent No.
US 12,601,873
App. No.
18/481,526
Granted
Apr 14, 2026
Kind
B2
Abstract

An optical connection structure includes a first silicon photonic chip having a first lateral surface, a second silicon photonic chip having a second lateral surface that faces the first lateral surface, and an optical waveguide disposed astride a gap between the first silicon photonic chip and the second silicon photonic chip. The first silicon photonic chip includes a first silicon substrate and a first silicon waveguide disposed over the first silicon substrate. The second silicon photonic chip includes a second silicon substrate and a second silicon waveguide disposed over the second silicon substrate. The optical waveguide includes a first cladding filling a space between the first lateral surface and the second lateral surface, a core disposed on the first cladding and covering one end of the first silicon waveguide and one end of the second silicon waveguide, and a cladding covering the core.

Claims (28)

1 . An optical connection structure comprising:

a first silicon photonic chip having a first lateral surface;

a second silicon photonic chip having a second lateral surface and disposed such that the second lateral surface faces the first lateral surface;

an optical waveguide disposed astride a gap between the first silicon photonic chip and the second silicon photonic chip; and

a support substrate,

wherein the first silicon photonic chip includes:

a first silicon substrate; and

a first silicon waveguide disposed over an upper surface of the first silicon substrate, the second silicon photonic chip includes:

a second silicon substrate; and

a second silicon waveguide disposed over an upper surface of the second silicon substrate, and

the optical waveguide includes:

a first cladding filling a space between the first lateral surface and the second lateral surface;

a core disposed on the first cladding and covering one end of the first silicon waveguide and one end of the second silicon waveguide, the core optically connecting the first silicon waveguide and the second silicon waveguide; and

a second cladding covering the core,

wherein a lower surface of the first silicon substrate is attached to an upper surface of the support substrate via a first adhesive layer, and a lower surface of the second silicon substrate is attached to the upper surface of the support substrate via a second adhesive layer, and

wherein the support substrate and the first silicon photonic chip are not electrically connected to each other, and the support substrate and the second silicon photonic chip are not electrically connected to each other.

2 . The optical connection structure as claimed in claim 1 , wherein a width of the one end of the first silicon waveguide narrows toward the first cladding in plan view, and a width of the one end of the second silicon waveguide narrows toward the first cladding in plan view.

3 . The optical connection structure as claimed in claim 1 , wherein the first silicon waveguide is disposed between a first protective film disposed on the first silicon substrate and a second protective film disposed on the first protective film, and the one end of the first silicon waveguide extends beyond the second protective film, and

wherein the second silicon waveguide is disposed between a third protective film disposed on the second silicon substrate and a fourth protective film disposed on the third protective film, and the one end of the second silicon waveguide extends beyond the fourth protective film.

4 . The optical connection structure as claimed in claim 3 , further comprising electrode pads for external connection disposed on the second protective film and the fourth protective film.

5 . The optical connection structure as claimed in claim 3 , wherein a surface of the first protective film on which the first silicon waveguide is disposed, a surface of the third protective film on which the second silicon waveguide is disposed, and a surface of the first cladding on which the core is disposed are flush with each other.

6 . The optical connection structure as claimed in claim 1 , wherein the first silicon photonic chip includes a light emitting device configured to emit light that is coupled into another end of the first silicon waveguide, and the second silicon photonic chip includes a light receiving device configured to receive light emitted from another end of the second silicon waveguide.

7 . The optical connection structure as claimed in claim 1 , wherein a plurality of said first silicon waveguides are disposed over the upper surface of the first silicon substrate, and a plurality of said second silicon waveguides are disposed over the upper surface of the second silicon substrate, and

wherein the optical waveguide includes a plurality of said cores each of which covers one end of a corresponding one of the first silicon waveguides and one end of a corresponding one of the second silicon waveguides and each of which optically connects a corresponding one of the first silicon waveguides and a corresponding one of the second silicon waveguides.

8 . An optical module comprising:

the optical connection structure of claim 1 ; and

an interconnect substrate,

wherein the first silicon photonic chip and the second silicon photonic chip are flip-chip mounted on the interconnect substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2023
From: YOSHIDA, KAZUHIRO
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 065136/0468 →
Priority Claims (1)
JP 2022-168205 · Oct 20, 2022 · national
Continuity (2)
Related Publication 20240134118A1 · Apr 25, 2024
Related Publication 20240230994A9 · Jul 11, 2024
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