IP Library Patent Application 18483261
Patent Application
App. No. 18/483,261

OPTIMAL FAULT-TOLERANT IMPLEMENTATIONS OF HEISENBERG INTERACTIONS AND CONTROLLED-Z^a GATES

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Patent No.
US None
App. No.
18/483,261
Abstract

The disclosure describes various aspects of techniques for optimal fault-tolerant implementations of controlled-Z α gates and Heisenberg interactions. Improvements in the implementation of the controlled-Z α gate can be made by using a clean ancilla and in-circuit measurement. Various examples are described that depend on whether the implementation is with or without measurement and feedforward. The implementation of the Heisenberg interaction can leverage the improved controlled-Z α gate implementation. These implementations can cut down significantly the implementation costs associated with fault-tolerant quantum computing systems.

Claims (49)

1 . A method for performing a quantum algorithm, comprising:

identifying use of a controlled-Z α gate for the quantum algorithm, wherein α is a parameter and αϵ[−1, 1], wherein the quantum algorithm includes a Heisenberg interaction and is based on projecting a real-valued degree of freedom in the Heisenberg interaction onto a R z α rotation;

implementing the controlled-Z α gate for a fault-tolerant quantum information processing (QIP) system, wherein the controlled-Z α gate includes multiple elements with only six (6) of the multiple elements being controlled-NOT (CNOT) gates;

mapping the implemented controlled-Z α gate into a physical representation in the fault-tolerant QIP system; and

performing the quantum algorithm that includes the Heisenberg interaction based at least in part on the physical representation.

2 . The method of claim 1 , wherein the implementing of the controlled-Z α gate includes implementing the controlled-Z α gate with an ancilla qubit for the fault-tolerant QIP system.

3 . The method of claim 2 , wherein the multiple elements of the controlled-Z α gate include a single parametrized Z α gate, only four (4) Hadamard gates, only four (4) T gates, only four (4) T † gates, and the six (6) controlled-NOT (CNOT) gates.

4 . The method of claim 1 , wherein the quantum algorithm is a quantum Fourier transform (QFT).

5 . The method of claim 1 , further comprising implementing the controlled-Z α gate without measurement and feedforward.

6 . The method of claim 1 , wherein:

the fault-tolerant QIP system is a trapped-ion QIP system, and

the mapping of the implemented controlled-Z α gate uses multiple qubits in the trapped-ion QIP system.

7 . The method of claim 1 , wherein:

the fault-tolerant QIP system is a superconducting QIP system, and

the mapping of the implemented controlled-Z α gate uses multiple superconducting-based qubits in the superconducting QIP system.

8 . A fault-tolerant quantum information processing (QIP) system for performing a quantum algorithm, comprising:

an implementation component configured to:

identify use of a controlled-Z α gate as part of the quantum algorithm, wherein α is a parameter and αϵ[−1, 1], wherein the quantum algorithm includes a Heisenberg interaction and is based on projecting a real-valued degree of freedom in the Heisenberg interaction onto a R z α rotation,

implement the controlled-Z α gate for the fault-tolerant quantum information processing (QIP) system, wherein the controlled-Z α gate includes multiple elements with only six (6) of the multiple elements being controlled-NOT (CNOT) gates;

map the implemented controlled-Z α gate into a physical representation in the fault-tolerant QIP system; and

an algorithms component configured to perform the quantum algorithm that includes the Heisenberg interaction based at least in part on the physical representation.

9 . The fault-tolerant QIP system of claim 8 , wherein the implementation component is further configured to implement the controlled-Z α gate with an ancilla qubit for the fault-tolerant QIP system.

10 . The fault-tolerant QIP system of claim 9 , wherein the multiple elements of the controlled-Z α gate include a single parametrized Z α gate, only four (4) Hadamard gates, only four (4) T gates, only four (4) T † gates, and the six (6) controlled-NOT (CNOT) gates.

11 . The fault-tolerant QIP system of claim 8 , wherein the quantum algorithm is a quantum Fourier transform (QFT).

12 . The fault-tolerant QIP system of claim 8 , wherein the implementation component is further configured to implement the controlled-Z α gate without measurement and feedforward.

13 . The fault-tolerant QIP system of claim 8 , wherein:

the fault-tolerant QIP system is a trapped-ion QIP system, and

the implementation component is further configured to map the implemented controlled-Z α gate using multiple qubits in the trapped-ion QIP system.

14 . The fault-tolerant QIP system of claim 8 , wherein:

the fault-tolerant QIP system is a superconducting QIP system, and

the implementation component is further configured to map the implemented controlled-Z α gate using multiple superconducting-based qubits in the superconducting QIP system.

15 . A fault-tolerant quantum information processing (QIP) system comprising:

electronic memory configured to store code for performing a quantum algorithm; and

a processor that, when executing the code stored on the electronic memory, is configured to:

identify use of a controlled-Z α gate for the quantum algorithm, wherein α is a parameter and αϵ[−1, 1], wherein the quantum algorithm includes a Heisenberg interaction and is based on projecting a real-valued degree of freedom in the Heisenberg interaction onto a R z α rotation,

implement the controlled-Z α gate for a fault-tolerant quantum information processing (QIP) system, wherein the controlled-Z α gate includes multiple elements with only six (6) of the multiple elements being controlled-NOT (CNOT) gates,

map the implemented controlled-Z α gate into a physical representation in the fault-tolerant QIP system, and

perform the quantum algorithm that includes the Heisenberg interaction based at least in part on the physical representation.

16 . The fault-tolerant QIP system of claim 15 ,

wherein the processor is further configured to implement the controlled-Z α gate with an ancilla qubit for the fault-tolerant QIP system, and

wherein the multiple elements of the controlled-Z α gate include a single parametrized Z α gate, only four (4) Hadamard gates, only four (4) T gates, only four (4) T † gates, and the six (6) controlled-NOT (CNOT) gates.

17 . The fault-tolerant QIP system of claim 15 , wherein the quantum algorithm is a quantum Fourier transform (QFT).

18 . The fault-tolerant QIP system of claim 15 , wherein the processor is further configured to implement the controlled-Z α gate without measurement and feedforward.

19 . The fault-tolerant QIP system of claim 8 , wherein:

the fault-tolerant QIP system is a trapped-ion QIP system, and

the processor is further configured to map the implemented controlled-Z α gate using multiple qubits in the trapped-ion QIP system.

20 . The fault-tolerant QIP system of claim 8 , wherein:

the fault-tolerant QIP system is a superconducting QIP system, and

the processor is further configured to map the implemented controlled-Z α gate using multiple superconducting-based qubits in the superconducting QIP system.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2023
From: NAM, YUNSEONG
To: IONQ, INC.
Reel/Frame 065173/0142 →
EMPLOYMENT AGREEMENT Recorded Oct 10, 2023
From: MASLOV, DMITRI
To: IONQ, INC.
Reel/Frame 065198/0134 →