NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a source region and a drain region disposed in a substrate, a gate stack including a floating gate and a control gate disposed between the source region and the drain region, a select gate insulating layer disposed on a sidewall of the gate stack, and a select gate disposed on the select gate insulating layer, the select gate having a height higher than a height of the gate stack or a height of the control gate.
1 . A semiconductor device comprising:
a source region and a drain region disposed in a substrate;
a gate stack comprising a floating gate and a control gate disposed between the source region and the drain region;
a select gate insulating layer disposed on a sidewall of the gate stack; and
a select gate disposed on the select gate insulating layer, the select gate having a height higher than a height of the gate stack or a height of the control gate.
2 . The semiconductor device of claim 1 , further comprising:
a select gate silicide layer disposed on the select gate; and
a control gate silicide layer disposed on the control gate, the control gate silicide layer having a lateral length smaller than a lateral length of the control gate.
3 . The semiconductor device of claim 2 , further comprising:
a first spacer disposed on a sidewall of the select gate, and disposed adjacent to the source region;
a second spacer disposed on an opposite sidewall of the select gate, and extending on a top surface of the gate stack; and
a third spacer disposed on an opposite sidewall of the gate stack, and disposed adjacent to the drain region.
4 . The semiconductor device of claim 3 , wherein the second spacer is disposed between the select gate silicide layer and the control gate silicide layer.
5 . The semiconductor device of claim 3 , wherein the second spacer contacts the select gate silicide layer, the control gate silicide layer and the control gate.
6 . The semiconductor device of claim 3 , wherein the second spacer has a height higher than a height of the first spacer or a height of the third spacer.
7 . A method for fabricating a semiconductor device, the method comprising:
forming a gate stack on a substrate, the gate stack comprising a floating gate and a control gate;
forming a select gate insulating layer on a sidewall of the gate stack;
forming a select gate on the select gate insulating layer, the select gate having a height higher than a height of the gate stack;
forming spacers on substrate, the spacers comprising:
a first spacer disposed on a sidewall of the select gate;
a second spacer disposed on an opposite sidewall of the select gate, and extending on a top surface of the gate stack;
a third spacer disposed on an opposite sidewall of the gate stack; and
forming a source region and a drain region adjacent to the first spacer and third spacer, respectively.
8 . The method of claim 7 , further comprising:
forming a stacked layer on the substrate;
forming a hard mask pattern on the stacked layer; and
performing an etching process to the stacked layer implemented by the hard mask pattern to form the gate stack.
9 . The method of claim 7 , further comprising:
forming a select gate silicide layer on the select gate; and
forming a control gate silicide layer on the control gate, the control gate silicide layer having a lateral length smaller than a lateral length of the control gate.
10 . The method of claim 9 , wherein the second spacer is disposed between the select gate silicide layer and the control gate silicide layer.
11 . The method of claim 7 , wherein the second spacer has a height higher than a height of the first spacer or a height of the third spacer.
12 . A method for fabricating a semiconductor device, the method comprising:
forming a gate stack on a substrate, the gate stack comprising a floating gate and a control gate;
forming a select gate insulating layer on a sidewall of the gate stack;
forming a select gate on the select gate insulating layer, the select gate having a first height higher than a height of the gate stack and a second height being similar to that of the gate stack;
forming lightly doped regions in the substrate;
forming spacers on substrate, the spacers comprising:
a first spacer disposed on a sidewall of the select gate;
a second spacer disposed on an opposite sidewall of the select gate, and extending on a top surface of the gate stack; and
a third spacer disposed on an opposite sidewall of the gate stack; and
forming a source region and a drain region adjacent to the first spacer and third spacer.
13 . The method of claim 12 , further comprising:
forming a select gate silicide layer on the select gate; and
forming a control gate silicide layer on the control gate, the control gate silicide layer having a lateral length smaller than a lateral length of the control gate.
14 . The method of claim 13 , further comprising:
depositing an interlayer insulating layer on the gate stack;
forming contact plugs in the interlayer insulating layer; and
electrically connecting metal wirings to the contact plugs.
15 . The method of claim 12 , wherein an upper surface area of the select gate is larger than that of the gate stack.