Granted Patent B2

US 12,276,885 · App. 18/484,434 · Granted Apr 15, 2025

Inventors: Yoonsung Um (Guangdong, CN); Shuang Wang (Guangdong, CN); Jinming Liu (Guangdong, CN); Fan Gao (Guangdong, CN); Wu Cao (Guangdong, CN); Hongyuan Xu (Guangdong, CN); Chungching Hsieh (Guangdong, CN)

Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

G02F1/134309G02F1/136286

Abstract

Claims (45)

1. An array substrate comprising:

a substrate; and

at least one pixel unit comprising:

at least one pixel group disposed on the substrate, each of the at least one pixel group comprising six sub-pixels arranged at intervals in a first direction, and each of the six sub-pixels comprising at least one pixel electrode; and

at least three data line groups disposed on the substrate, the at least three data line groups comprising three data line groups, each of the three data line groups corresponding to the at least one pixel electrode of one of the six sub-pixels, and each of the three data line groups being located on one side of the at least one pixel electrode which is adjacent to the substrate;

wherein each of the three data line groups comprises two data lines arranged at intervals in the first direction, and the at least one pixel electrode of each of the six sub-pixels is electrically connected to a respective one of the two data lines of a corresponding one of the three data line groups;

wherein the six sub-pixels comprise two first color sub-pixels, two second color sub-pixels, and two third color sub-pixels: one of the three data line groups and one of the two first color sub-pixels are arranged correspondingly, other two of the three data line groups and the two second color sub-pixels are arranged correspondingly respectively, and the two data lines of each of the three data line groups are each electrically connected to the at least one pixel electrode of a corresponding one of two, which are of a same color, of the six sub-pixels.

2. The array substrate according to claim 1 , wherein each of the at least one pixel electrode comprises a first backbone electrode extending in a second direction, and the first backbone electrode and a corresponding one of the three data line groups are disposed oppositely.

3. The array substrate according to claim 2 , wherein an orthographic projection of the first backbone electrode on the substrate covers an orthographic projection of the corresponding one of the three data line groups on the substrate.

4. The array substrate according to claim 2 , wherein the first backbone electrode comprises:

a first sub-portion corresponding to one of the two data lines of the corresponding one of the three data line groups; and

a second sub-portion corresponding to an other one of the two data lines of the corresponding one of the three data line groups.

5. The array substrate according to claim 4 , wherein each of the at least one pixel electrode further comprises a second backbone electrode extending in the first direction, and the first sub-portion and the second sub-portion are both electrically connected to the second backbone electrode.

6. The array substrate according to claim 4 , wherein the two data lines of each of the three data line groups are of polyline shapes.

7. The array substrate according to claim 1 , wherein each of the six sub-pixels further comprises at least one transistor electrically connected to the at least one pixel electrode of a respective one of the six sub-pixels, the at least one transistor is electrically connected to a respective one of the two data lines of a corresponding one of the three data line groups;

for each of the at least one pixel group, the at least one transistor of each of ones of the six sub-pixels is located on a first side of the pixel group, and the at least one transistor of each of other ones of the six sub-pixels is located on a second side of the pixel group, and the first side is opposite to the second side.

8. The array substrate according to claim 7 , further comprising a first gate scan line and a second gate scan line extending in the first direction, wherein the first gate scan line is electrically connected to a gate of the at least one transistor of each of the ones of the six sub-pixels on the first side, and the second gate scan line is electrically connected to a gate of the at least one transistor of each of the other ones of the six sub-pixels on the second side.

9. The array substrate according to claim 7 , wherein the at least one pixel group comprises a plurality of pixel groups arranged at intervals in a second direction; the array substrate further comprises third gate scan lines extending in the first direction, and every adjacent two of the plurality of pixel groups share one of the third gate scan lines.

10. The array substrate according to claim 1 , further comprising a plurality of common electrode lines extending in a second direction, wherein the plurality of common electrode lines are disposed in a same layer as the two data lines of each of the three data line groups, and each of the common electrode lines is disposed a gap between every adjacent two of the six sub-pixels.

11. An array substrate, comprising:

a substrate; and

at least one pixel unit comprising:

at least one pixel group disposed on the substrate, each of the at least one pixel group comprising six sub-pixels arranged at intervals in a first direction, and each of the six sub-pixels comprising at least one pixel electrode; and

at least three data line groups disposed on the substrate, the at least three data line groups comprising three data line groups, each of the three data line groups corresponding to the at least one pixel electrode of one of the six sub-pixels, and each of the three data line groups being located on one side of the at least one pixel electrode which is adjacent to the substrate;

wherein each of the three data line groups comprises two data lines arranged at intervals in the first direction, and the at least one pixel electrode of each of the six sub-pixels is electrically connected to a respective one of the two data lines of a corresponding one of the three data line groups;

wherein the six sub-pixels comprise two first color sub-pixels, two second color sub-pixels, and two third color sub-pixels: one of the three data line groups and one of the two first color sub-pixels are arranged correspondingly, other two of the three data line groups and the two second color sub-pixels are arranged correspondingly respectively, and the two data lines of each of the three data line groups are each electrically connected to the at least one pixel electrode of a corresponding one of two, which are of a same color, of the six sub-pixels;

wherein voltage polarities of the two data lines of each of the three data line groups are different.

12. The array substrate according to claim 1 , wherein the two first color sub-pixels are blue sub-pixels, the two second color sub-pixels are green sub-pixels, and the two third color sub-pixels are red sub-pixels; the three data line groups comprise a first data line group, a second data line group, and a third data line group; the first data line group and one of the two first color sub-pixels are arranged correspondingly; the second data line group and the third data line group, and the two second color sub-pixels are arranged correspondingly respectively; the two data lines of the first data line group are each electrically connected to the at least one pixel electrode of a corresponding one of the two second color sub-pixels, the two data lines of the second data line group are each electrically connected to the at least one pixel electrode of a corresponding one of the two third color sub-pixels, and the two data lines of the third data line group are each electrically connected to the at least one pixel electrode of a corresponding one of the two first color sub-pixels.

13. The array substrate according to claim 12 , wherein one of the two first color sub-pixels and one of the two second color sub-pixels are adjacent to the two third color sub-pixels and located between the two third color sub-pixels, the one of the two first color sub-pixels and one of the two third color sub-pixels are adjacent to the two second color sub-pixels and located between the two second color sub-pixels; an other one of the two second color sub-pixels and the one of the two third color sub-pixels are adjacent to the two first color sub-pixels and located between the two first color sub-pixels;

for each of the two first color sub-pixels, each of the two second color sub-pixels and each of the two third color sub-pixels, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are sequentially arranged at intervals in the first direction.

14. The array substrate according to claim 13 , wherein the at least three data line groups further comprise a fourth data line group, the fourth data line group and an other one of the two first color sub-pixels are arranged correspondingly, and the fourth data line group has a same structure as the first data line group.

15. A display panel comprising an array substrate, the array substrate comprising:

a substrate; and

at least one pixel unit comprising:

at least one pixel group disposed on the substrate, each of the at least one pixel group comprising six sub-pixels arranged at intervals in a first direction, and each of the six sub-pixels comprising at least one pixel electrode; and

at least three data line groups disposed on the substrate, the at least three data line groups comprising three data line groups, each of the three data line groups corresponding to the at least one pixel electrode of one of the six sub-pixels, and each of the three data line groups being located on one side of the at least one pixel electrode which is adjacent to the substrate;

wherein each of the three data line groups comprises two data lines arranged at intervals in the first direction, and the at least one pixel electrode of each of the six sub-pixels is electrically connected to a respective one of the two data lines of a corresponding one of the three data line groups,

wherein the six sub-pixels comprise two first color sub-pixels, two second color sub-pixels, and two third color sub-pixels: one of the three data line groups and one of the two first color sub-pixels are arranged correspondingly, other two of the three data line groups and the two second color sub-pixels are arranged correspondingly respectively, and the two data lines of each of the three data line groups are each electrically connected to the at least one pixel electrode of a corresponding one of two, which are of a same color, of the six sub-pixels.

16. The display panel according to claim 15 , wherein each of the at least one pixel electrode comprises a first backbone electrode extending in a second direction, and the first backbone electrode and a corresponding one of the three data line groups are disposed oppositely.

17. The display panel according to claim 16 , wherein an orthographic projection of the first backbone electrode on the substrate covers an orthographic projection of the corresponding one of the three data line groups on the substrate.

18. The display panel according to claim 16 , wherein the first backbone electrode comprises:

a first sub-portion corresponding to one of the two data lines of the corresponding one of the three data line groups; and

a second sub-portion corresponding to an other one of the two data lines of the corresponding one of the three data line groups.

19. The display panel according to claim 18 , wherein each of the at least one pixel electrode further comprises a second backbone electrode extending in the first direction, and the first sub-portion and the second sub-portion are both electrically connected to the second backbone electrode.

20. The display panel according to claim 18 , wherein the two data lines of each of the three data line groups are of polyline shapes.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (14)