Granted Patent B2

US 12,417,724 · App. 18/488,294 · Granted Sep 16, 2025

Inventors: Jaesung Lee (Suwon-si, KR); Kyounghwan Kwon (Suwon-si, KR); Jongkon Bae (Suwon-si, KR); Donghwy Kim (Suwon-si, KR); Byungduk Yang (Suwon-si, KR)

Assignee: Samsung Electronics Co., Ltd.

G09G3/20G09G2230/00G09G2310/0264G09G2310/08G09G2330/021G09G2340/0435

Abstract

Claims (72)

1. An electronic device comprising:

at least one processor comprising processing circuitry;

memory comprising one or more storage media storing instructions;

a display including display driver circuitry and a display panel;

a first path, connecting the display driver circuitry to the at least one processor, configured to transmit an image from the at least one processor to the display driver circuitry; and

a second path, connecting the display driver circuitry to the at least one processor, separated from the first path,

wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:

periodically transmit, via the second path, from the at least one processor to the display driver circuitry, a pulse signal to synchronize counting of the at least one processor performed for displaying an image on the display panel with counting of the display driver circuitry performed for displaying an image on the display panel;

in response to a start timing of a first synchronization signal for the at least one processor being identified as not overlapping a start timing of a second synchronization signal for the at least one processor in accordance with the counting of the at least one processor, set a waveform of the pulse signal periodically transmitted as a first waveform; and

in response to a start timing of the first synchronization signal for the at least one processor being identified as overlapping a start timing of the second synchronization signal for the at least one processor in accordance with the counting of the at least one processor, set the waveform of the pulse signal periodically transmitted as a second waveform different from the first waveform, and

wherein a cycle of the first synchronization signal for the at least one processor is shorter than a cycle of the second synchronization signal for the at least one processor.

2. The electronic device of claim 1 , wherein the first path is configured to be disabled in at least portion of a time period that ceases to transmit an image from the at least one processor to the display driver circuitry, and

wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to

maintain, while the first path is disabled, the pulse signal periodically transmitted via the second path from the at least one processor to the display driver circuitry.

3. The electronic device of claim 1 , wherein the display driver circuitry includes a graphic random access memory (GRAM),

wherein the first path is configured to be disabled in at least portion of a time period that executes displaying on the display panel by scanning, by the display driver circuitry, an image stored in the GRAM, and

wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to maintain, while the first path is disabled, the pulse signal periodically transmitted via the second path from the at least one processor to the display driver circuitry.

4. The electronic device of claim 1 , wherein the display driver circuitry is configured to:

based on the waveform of the pulse signal periodically transmitted from the at least one processor to the display driver circuitry being identified as the first waveform, synchronize the first synchronization signal for the display driver circuitry with the first synchronization signal for the at least one processor; and

based on the waveform of the pulse signal periodically transmitted from the at least one processor to the display driver circuitry being identified as the second waveform, synchronize the second synchronization signal for the display driver circuitry with the second synchronization signal for the at least one processor.

5. The electronic device of claim 1 , wherein the first synchronization signal for the at least one processor comprises a horizontal synchronization signal for the at least one processor, and

wherein the second synchronization signal for the at least one processor comprises a vertical synchronization signal for the at least one processor.

6. The electronic device of claim 1 , wherein the first synchronization signal for the at least one processor comprises a horizontal synchronization signal for the at least one processor, and

wherein the second synchronization signal for the at least one processor comprises an emission synchronization signal for the at least one processor indicating a transmission timing of an emission signal from the display driver circuitry to the display panel.

7. The electronic device of claim 1 , wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:

set the waveform of the pulse signal periodically transmitted as the first waveform by setting a width of the pulse signal as a first width; and

set the waveform of the pulse signal periodically transmitted as the second waveform by setting the width of the pulse signal as a second width different from the first width.

8. The electronic device of claim 1 ,

wherein a transmission cycle of the pulse signal periodically transmitted corresponds to the cycle of the first synchronization signal for the at least one processor.

9. The electronic device of claim 1 , wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:

identify a control command to be provided to the display driver circuitry with respect to displaying an image on the display panel; and

based on the identification, provide the control command to the display driver circuitry by setting the waveform of the pulse signal periodically transmitted as a third waveform different from the first waveform and the second waveform.

10. The electronic device of claim 9 , wherein the display driver circuit includes a graphic random access memory (GRAM), and

wherein the control command comprises a control command indicating to store an image in the GRAM and/or a control command indicating to change a refresh rate of an image to be displayed on the display panel.

11. An electronic device comprising:

at least one processor comprising processing circuitry;

a display including display driver circuitry and a display panel;

a first path, connecting the display driver circuitry to the at least one processor, configured to transmit an image from the at least one processor to the display driver circuitry; and

a second path, connecting the display driver circuitry to the at least one processor, separated from the first path,

wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:

periodically transmit, via the second path, from the at least one processor to the display driver circuitry, a pulse signal to synchronize counting of the at least one processor performed for displaying an image on the display panel; with counting of the display driver circuitry performed for displaying an image on the display panel;

identify a control command to be provided to the display driver circuit with respect to the display of the image on the display panel;

based on the identification, provide the control command to the display driver circuitry by changing a waveform of the pulse signal periodically transmitted from a first waveform to a second waveform different from the first waveform;

based on providing the control command to the display driver circuitry, restore the waveform of the pulse signal periodically transmitted to the first waveform.

12. The electronic device of claim 11 , wherein the display driver circuit includes a graphic random access memory (GRAM), and

wherein the control command comprises a control command indicating storing an image in the GRAM.

13. The electronic device of claim 11 , wherein the control command comprises a control command indicating changing a refresh rate of an image to be displayed on the display panel.

14. The electronic device of claim 11 , wherein the first path is configured to be disabled in at least portion of a time period that ceases to transmit an image from the at least one processor to the display driver circuitry, and

wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to maintain the pulse signal periodically transmitted via the second path from the at least one processor to the display driver circuitry, while the first path is disabled.

15. The electronic device of claim 11 , wherein the display driver circuit includes a graphic random access memory (GRAM),

wherein the first path is configured to be disabled in at least portion of a time period that executes displaying on the display panel by scanning, by the display driver circuitry, an image stored in the GRAM, and

wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to maintain, while the first path is disabled, the pulse signal periodically transmitted via the second path from the at least one processor to the display driver circuitry.

16. The electronic device of claim 11 , wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:

in response to a start timing of a first synchronization signal for the at least one processor being identified as not overlapping a start timing of a second synchronization signal for the at least one processor in accordance with the counting of the at least one processor, set the waveform of the pulse signal periodically transmitted as the first waveform; and

in response to a start timing of the first synchronization signal for the at least one processor being identified as overlapping a start timing of the second synchronization signal for the at least one processor in accordance with the counting of the at least one processor, set the waveform of the pulse signal periodically transmitted as a third waveform different from the first waveform and the second waveform, and

wherein a cycle of the first synchronization signal for the at least one processor is shorter than a cycle of the second synchronization signal for the at least one processor.

17. The electronic device of claim 16 , wherein the display driver circuitry is configured to:

based on the waveform of the pulse signal periodically transmitted from the at least one processor to the display driver circuitry being identified as the first waveform, synchronize the first synchronization signal for the display driver circuitry with the first synchronization signal for the at least one processor; and

based on the waveform of the pulse signal periodically transmitted from the at least one processor to the display driver circuitry being identified as the third waveform, synchronize the second synchronization signal for the display driver circuitry with the second synchronization signal for the at least one processor.

18. The electronic device of claim 17 , wherein the first synchronization signal for the at least one processor comprises a horizontal synchronization signal for the at least one processor, and

wherein the second synchronization signal for the at least one processor comprises a vertical synchronization signal for the at least one processor.

19. The electronic device of claim 18 , wherein the control command is provided before a start timing of the vertical synchronization signal for the at least one processor used for displaying an image to which the control command is to be applied.

20. An electronic device comprising:

at least one processor comprising processing circuitry;

memory comprising one or more storage media storing instructions;

a display including display driver circuitry and a display panel;

a first path, connecting the display driver circuitry to the at least one processor, configured to transmit an image from the at least one processor to the display driver circuitry; and

a second path, connecting the display driver circuitry to the at least one processor, separated from the first path,

wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to:

periodically transmit, via the second path, from the at least one processor to the display driver circuitry, a pulse signal to synchronize counting of the at least one processor performed for displaying an image on the display panel with counting of the display driver circuitry performed for displaying an image on the display panel, wherein a transmission cycle of the pulse signal periodically transmitted corresponds to a cycle of a first synchronization signal for the at least one processor;

based on a start timing of the first synchronization signal for the at least one processor being identified as not overlapping a start timing of a second synchronization signal for the at least one processor in accordance with the counting of the at least one processor, maintain a waveform of the pulse signal periodically transmitted as a first waveform; and

based on a start timing of the first synchronization signal for the at least one processor being identified as overlapping a start timing of the second synchronization signal for the at least one processor in accordance with the counting of the at least one processor, change the waveform of the pulse signal periodically transmitted to a second waveform different from the first waveform.

Assignments (1)

Priority Claims (6)

Continuity (2)

References Cited (70)