Low dropout regulators
A low dropout regulator can comprise a driver configured to receive a first input voltage and generates an output voltage, an error amplifier configured to receive a second input voltage having a magnitude different from the first input voltage and output an amplifier output voltage based on the difference between a feedback voltage corresponding to the output voltage and a reference voltage, and a driving controller configured to control the output voltage of the driver based on the amplifier output voltage.
1 . A low dropout regulator, comprising:
a driver configured to receive a first input voltage and generate an output voltage;
an error amplifier configured to receive a second input voltage having a magnitude different from the first input voltage and output an amplifier output voltage based on a difference between a feedback voltage corresponding to the output voltage and a reference voltage; and
a driving controller configured to control the output voltage of the driver based on the amplifier output voltage,
wherein the driver comprises a driving transistor,
wherein a signal corresponding to the amplifier output voltage is configured to be input to a gate terminal of the driving transistor, and
wherein the driving controller comprises:
a switching circuit connected between an output line of the error amplifier and the gate terminal of the driving transistor;
a first PMOS transistor comprising one terminal connected to a supply line that is configured to supply the first input voltage; and
a second PMOS transistor comprising one terminal connected to another terminal of the first PMOS transistor and another terminal connected between the switching circuit and the gate terminal of the driving transistor.
2 . The low dropout regulator of claim 1 , wherein the first input voltage and the second input voltage are configured to be transmitted from a power management integrated circuit, respectively.
3 . The low dropout regulator of claim 1 , wherein the magnitude of the second input voltage is greater than a magnitude of the first input voltage.
4 . The low dropout regulator of claim 1 , wherein the second input voltage is configured to be supplied to the error amplifier after the first input voltage is supplied to the driver.
5 . The low dropout regulator of claim 1 , wherein the driving controller comprises:
an NMOS transistor comprising one terminal connected to the supply line that is configured to supply the first input voltage and another terminal connected between the switching circuit and the gate terminal of the driving transistor.
6 . The low dropout regulator of claim 5 , wherein the driving controller comprises:
a pull-up element connected in parallel with the NMOS transistor.
7 . The low dropout regulator of claim 5 , wherein the switching circuit is configured to be controlled to be open after the first input voltage is supplied to the driver and before the second input voltage is supplied to the error amplifier.
8 . The low dropout regulator of claim 1 , wherein the driving controller comprises:
an NMOS transistor comprising one terminal connected between the first PMOS transistor and the second PMOS transistor, and another terminal connected to ground.
9 . A low dropout regulator, comprising:
a driver configured to receive a first input voltage and generate an output voltage;
an error amplifier configured to receive a second input voltage having a magnitude different from the first input voltage and output an amplifier output voltage based on a difference between a feedback voltage corresponding to the output voltage and a reference voltage; and
a driving controller configured to control the output voltage of the driver based on the amplifier output voltage,
wherein the driving controller comprises:
a switching circuit connected between an output line of the error amplifier and a gate terminal of a driving transistor;
a first PMOS transistor comprising one terminal connected to a supply line that is configured to supply the first input voltage; and
a second PMOS transistor comprising one terminal connected to another terminal of the first PMOS transistor and another terminal connected between the switching circuit and the gate terminal of the driving transistor.
10 . The low dropout regulator of claim 9 , wherein the first input voltage and the second input voltage are configured to be transmitted from a power management integrated circuit, respectively.
11 . The low dropout regulator of claim 9 , wherein the magnitude of the second input voltage is greater than a magnitude of the first input voltage.
12 . The low dropout regulator of claim 9 , wherein the second input voltage is configured to be supplied to the error amplifier after the first input voltage is supplied to the driver.
13 . The low dropout regulator of claim 9 , wherein the driver comprises the driving transistor, and
wherein a signal corresponding to the amplifier output voltage is configured to be input to a gate terminal of the driving transistor.
14 . The low dropout regulator of claim 9 , wherein the switching circuit is configured to be controlled to be open after the first input voltage is supplied to the driver and before the second input voltage is supplied to the error amplifier.
15 . The low dropout regulator of claim 9 , wherein the driving controller comprises:
an NMOS transistor comprising one terminal connected between the first PMOS transistor and the second PMOS transistor and another terminal connected to ground.
16 . A low dropout regulator, comprising:
a driver configured to receive a first input voltage and generate an output voltage;
an error amplifier configured to receive a second input voltage having a magnitude different from the first input voltage and output an amplifier output voltage based on a difference between a feedback voltage corresponding to the output voltage and a reference voltage;
a first PMOS transistor comprising one terminal connected to a supply line that is configured to supply the first input voltage; and
a second PMOS transistor comprising one terminal connected to another terminal of the first PMOS transistor and another terminal connected to a gate terminal of a driving transistor included in the driver.
17 . The low dropout regulator of claim 16 , wherein the second input voltage is configured to be supplied to the error amplifier after the first input voltage is supplied to the driver.