Techniques for optimizing store of common values to memory structures
Disclosed are techniques for optimizing store of common values to memory structures. In an aspect, a method for instruction decoding may include obtaining a store instruction that involves two or more registers. The method may include determining that at least one register of the two or more registers comprises an all-zeros value. The method may also include decoding the store instruction into a store-zeros micro-operation based at least in part on the determining. In some examples of the method, zeros-indicating metadata may be used to indicate that an all-zeros value has been stored in a memory structure.
1 . A method for instruction decoding, comprising:
obtaining a store instruction that involves two or more registers;
determining that at least one register of the two or more registers comprises an all-zeros value; and
decoding the store instruction to include a store-zeros micro-operation based at least in part on the determining.
2 . The method of claim 1 , wherein a first number of registers used by the store-zeros micro-operation is fewer than a second number of the two or more registers of the store instruction.
3 . The method of claim 2 , wherein the first number is two and the second number is three.
4 . The method of claim 1 , wherein:
a first register of the two or more registers is encoded in a first instruction field of the store instruction and comprises a first value to be stored in a cache memory,
a second register of the two or more registers is encoded in a second instruction field of the store instruction and comprises a second value to be stored in the cache memory, and
a third register of the two or more registers is encoded in a third instruction field of the store instruction and comprises a base register value.
5 . The method of claim 4 , wherein the store-zeros micro-operation uses the third register as a first source register and the first register as a second source register for executing the store-zeros micro-operation.
6 . The method of claim 5 , wherein:
the store instruction comprises a store pair of registers (STP) instruction, and
the store-zeros micro-operation is a single memory-based micro-operation decoded for the STP instruction.
7 . The method of claim 4 , further comprising:
scheduling the store-zeros micro-operation for execution;
calculating a memory address based at least in part on the base register value; and
storing, based at least in part on executing the store-zeros micro-operation, an all-zeros value in the cache memory corresponding to the calculated memory address.
8 . The method of claim 1 , further comprising:
scheduling the store-zeros micro-operation for execution;
storing, based at least in part on executing the store-zeros micro-operation, an all-zeros value in a store queue register of a cache memory; and
setting zeros-indicating metadata to indicate that the store queue register includes the all-zeros value.
9 . The method of claim 8 , further comprising:
refraining from accessing the store queue register for a micro-operation executed subsequent to the store-zeros micro-operation based at least in part on the zeros-indicating metadata.
10 . The method of claim 8 , wherein,
the zeros-indicating metadata comprises one or more indicator bits, and
a number of the one or more indicator bits is fewer than a number of bits in a cache line of a data element corresponding to the store queue register.
11 . The method of claim 1 , wherein the determining that the at least one register of the two or more registers comprises the all-zeros value is based at least in part on detecting, in the store instruction, a mnemonic associated with the at least one register.
12 . The method of claim 11 , wherein the mnemonic comprises a zero register (XZR) mnemonic.
13 . A processing unit, comprising:
a plurality of registers; and
one or more processors communicatively coupled to the plurality of registers and to communicate with one or more memories, the one or more processors, either alone or in combination, configured to:
obtain a store instruction that involves two or more registers;
determine that at least one register of the two or more registers comprises an all-zeros value; and
decode the store instruction to include a store-zeros micro-operation based at least in part on a determination that the at least one register of the two or more registers comprises the all-zeros value.
14 . The processing unit of claim 13 , wherein:
a first register of the two or more registers is encoded in a first instruction field of the store instruction and comprises a first value to be stored in a cache memory,
a second register of the two or more registers is encoded in a second instruction field of the store instruction and comprises a second value to be stored in the cache memory, and
a third register of the two or more registers is encoded in a third instruction field of the store instruction and comprises a base register value.
15 . The processing unit of claim 13 , wherein the one or more processors, either alone or in combination, are further configured to:
schedule the store-zeros micro-operation for execution;
store, based at least in part on executing the store-zeros micro-operation, an all-zeros value in a store queue register of a cache memory; and
set zeros-indicating metadata to indicate that the store queue register includes the all-zeros value.
16 . The processing unit of claim 15 , wherein the one or more processors, either alone or in combination, are further configured to:
refrain from accessing the store queue register for a micro-operation executed subsequent to the store-zeros micro-operation based at least in part on the zeros-indicating metadata.
17 . The processing unit of claim 15 , wherein:
the zeros-indicating metadata comprises one or more indicator bits, and
a number of the one or more indicator bits is fewer than a number of bits in a cache line of a data element corresponding to the store queue register.
18 . The processing unit of claim 13 , wherein the one or more processors, either alone or in combination, configured to determine that the at least one register of the two or more registers comprises the all-zeros value, are further configured to determine that the at least one register of the two or more registers comprises the all-zeros value based at least in part on detecting, in the store instruction, a mnemonic associated with the at least one register.
19 . A non-transitory computer-readable medium storing computer-executable instructions that, when executed by a processing unit, cause the processing unit to:
obtain a store instruction that involves two or more registers;
determine that at least one register of the two or more registers comprises an all-zeros value; and
decode the store instruction to include a store-zeros micro-operation based at least in part on a determination that the at least one register of the two or more registers comprises the all-zeros value.
20 . The method of claim 1 , wherein the store-zeros micro-operation stores an all-zeros value to memory without reading at least one register of the two or more registers from which the store instruction would otherwise obtain data to be stored.