IP Library Granted Patent US 12,550,263
Granted Patent B2
US 12,550,263 · App. 18/491,456 · Granted Feb 10, 2026

Switching oscillation reduction for power semiconductor device modules

Inventors: Oseob Jeon (Seoul, KR); Seungwon Im (Bucheon, KR); Rajani Kumar Thirukoluri (Munich, DE); Roveendra Paul (Dublin, CA)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H05K1/18H05K1/11H05K2201/10166
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Quick Facts
Patent No.
US 12,550,263
App. No.
18/491,456
Granted
Feb 10, 2026
Kind
B2
Abstract

In a general aspect, a half-bridge circuit includes a substrate having first, second and third patterned metal layers disposed on a surface. The circuit also includes first and second high-side transistors disposed on the first patterned metal layer, and first and conductive clips electrically coupling, respectively, the first and second high-side transistors with the second patterned metal layer. The circuit also includes first and second low-side transistors disposed on the second patterned metal layer, and third and fourth conductive clips electrically coupling, respectively, the first and second low-side transistors with the third patterned metal layer. The circuit further includes a DC+ terminal electrically coupled with the first patterned metal layer via a first conductive post disposed between the first and second high-side transistors, and a DC− terminal electrically coupled with the third patterned metal layer via a second conductive post disposed between the third and fourth conductive clips.

Claims (116)

1 . A half-bridge circuit power module comprising:

a substrate including a first patterned metal layer, a second patterned metal layer, and a third patterned metal layer disposed on a surface of the substrate;

a first high-side transistor and a second high-side transistor disposed on the first patterned metal layer;

a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer;

a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer;

a first low-side transistor and a second low-side transistor disposed on the second patterned metal layer;

a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer;

a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer;

a DC+ terminal that is electrically coupled with the first patterned metal layer via a first conductive post disposed between the first high-side transistor and the second high-side transistor on the first patterned metal layer; and

a DC− terminal that is electrically coupled with the third patterned metal layer via a second conductive post disposed between the third conductive clip and the fourth conductive clip on the third patterned metal layer.

2 . The half-bridge circuit power module of claim 1 , wherein the second patterned metal layer is electrically coupled with an output terminal of the half-bridge circuit power module via a third conductive post.

3 . The half-bridge circuit power module of claim 2 , wherein:

the first conductive clip electrically couples a source terminal of the first high-side transistor with the output terminal;

the second conductive clip electrically couples a source terminal of the second high-side transistor with the output terminal;

the third conductive clip electrically couples a source terminal of the first low-side transistor with the DC− terminal; and

the fourth conductive clip electrically couples a source terminal of the second low-side transistor with the DC− terminal.

4 . The half-bridge circuit power module of claim 2 , wherein:

the DC+ terminal, the DC− terminal and the output terminal include a first conductive material; and

the first conductive post, the second conductive post, and the third conductive post include a second conductive material different from the first conductive material.

5 . The half-bridge circuit power module of claim 4 , wherein:

the first conductive material is a metal; and

the second conductive material is an alloy of the metal.

6 . The half-bridge circuit power module of claim 4 , wherein:

the first conductive material is pure copper; and

the second conductive material is an alloy of copper including at least one of iron, or phosphorus.

7 . The half-bridge circuit power module of claim 1 , wherein:

the DC+ terminal is a first DC+ terminal; and

the substrate further includes:

a fourth patterned metal layer disposed on the surface of the substrate; and

a fifth patterned metal layer disposed on the surface of the substrate, the half-bridge circuit power module further comprising:

a third high-side transistor having a drain terminal disposed on the fourth patterned metal layer;

a fourth high-side transistor having a drain terminal disposed on the fourth patterned metal layer;

a fifth conductive clip electrically coupling a source terminal of the third high-side transistor with the fifth patterned metal layer;

a sixth conductive clip electrically coupling the fourth high-side transistor with the fifth patterned metal layer;

a second DC+ terminal that is electrically coupled with the fourth patterned metal layer via a third conductive post disposed between the third high-side transistor and the fourth high-side transistor.

8 . The half-bridge circuit power module of claim 7 , further comprising an output terminal that is:

electrically coupled with the second patterned metal layer via a fourth conductive post; and

electrically coupled with the fifth patterned metal layer via a fifth conductive post.

9 . The half-bridge circuit power module of claim 1 , wherein the substrate further includes a fourth patterned metal layer disposed on the surface of the substrate, the half-bridge circuit power module further comprising:

a third low-side transistor disposed on the fourth patterned metal layer; and

a fourth low-side transistor disposed on the fourth patterned metal layer,

the third conductive clip further electrically coupling the third low-side transistor to the third patterned metal layer,

the fourth conductive clip further electrically coupling the fourth low-side transistor to the third patterned metal layer.

10 . The half-bridge circuit power module of claim 9 , further comprising:

a fifth low-side transistor disposed on the second patterned metal layer;

a sixth low-side transistor disposed on the fourth patterned metal layer; and

a fifth conductive clip electrically coupling the fifth low-side transistor and the sixth low-side transistor with the third patterned metal layer,

the DC− terminal being further electrically coupled with the third patterned metal layer via a third conductive post disposed between the fourth conductive clip and the fifth conductive clip on the third patterned metal layer.

11 . The half-bridge circuit power module of claim 10 , wherein:

the DC+ terminal is a first DC+ terminal; and

the substrate further includes a fifth patterned metal layer disposed on the surface of the substrate,

the half-bridge circuit power module further comprising:

a third high-side transistor disposed on the first patterned metal layer;

a sixth conductive clip electrically coupling the third high-side transistor with the second patterned metal layer;

a fourth high-side transistor disposed on the fifth patterned metal layer;

a seventh conductive clip electrically coupling the fourth high-side transistor with the fourth patterned metal layer;

a fifth high-side transistor disposed on the fifth patterned metal layer;

an eighth conductive clip electrically coupling the fifth high-side transistor with the fourth patterned metal layer;

a sixth high-side transistor disposed on the fifth patterned metal layer;

a ninth conductive clip electrically coupling the sixth high-side transistor with the fourth patterned metal layer; and

a second DC+ terminal that is electrically coupled with fifth patterned metal layer via:

a third conductive post disposed between the fourth high-side transistor and the fifth high-side transistor on the fifth patterned metal layer; and

a fourth conductive post disposed between the fifth high-side transistor and the sixth high-side transistor on the fifth patterned metal layer,

the first DC+ terminal being further electrically coupled with the first patterned metal layer via fifth conductive post disposed between the second high-side transistor and the third high-side transistor on the first patterned metal layer.

12 . The half-bridge circuit power module of claim 1 , wherein:

respective drain terminals of the first high-side transistor and the second high-side transistor are disposed on and electrically coupled with the first patterned metal layer; and

respective drain terminals of the first low-side transistor and the second low-side transistor are disposed on and electrically coupled with the second patterned metal layer.

13 . A half-bridge circuit power module comprising:

a substrate including a first patterned metal layer, a second patterned metal layer, a third patterned metal layer, a fourth patterned metal layer, and a fifth patterned metal layer disposed on a surface of the substrate;

a first low-side transistor disposed on the first patterned metal layer and electrically coupled with the fifth patterned metal layer via a first conductive clip;

a second low-side transistor disposed on the first patterned metal layer and electrically coupled with the fifth patterned metal layer via a second conductive clip;

a third low-side transistor disposed on the second patterned metal layer and electrically coupled with the fifth patterned metal layer via the first conductive clip;

a fourth low-side transistor disposed on the second patterned metal layer and electrically coupled with the fifth patterned metal layer via the second conductive clip;

a first high-side transistor disposed on the third patterned metal layer and electrically coupled with the first patterned metal layer via a third conductive clip;

a second high-side transistor disposed on the third patterned metal layer and electrically coupled with the first patterned metal layer via a fourth conductive clip;

a third high-side transistor disposed on the fourth patterned metal layer and electrically coupled with the second patterned metal layer via a fifth conductive clip;

a fourth high-side transistor disposed on the fourth patterned metal layer and electrically coupled with the second patterned metal layer via a sixth conductive clip;

a first DC+ terminal electrically coupled with the third patterned metal layer via a first conductive post disposed between the first high-side transistor and the second high-side transistor on the third patterned metal layer;

a second DC+ terminal electrically coupled with the fourth patterned metal layer via a second conductive post disposed between the third high-side transistor and the fourth high-side transistor on the fourth patterned metal layer; and

a DC− terminal electrically coupled with the fifth patterned metal layer via a third conductive post disposed between the first conductive clip and the second conductive clip on the fifth patterned metal layer.

14 . The half-bridge circuit power module of claim 13 , further comprising an output terminal that is:

coupled with the first patterned metal layer via a fourth conductive post; and

coupled with the second patterned metal layer via a fifth conductive post.

15 . The half-bridge circuit power module of claim 14 , wherein:

the first DC+ terminal, the second DC+ terminal and the output terminal include pure copper; and

the first conductive post, the second conductive post, the third conductive post, the fourth conductive post, and the fifth conductive post include an alloy of copper.

16 . The half-bridge circuit power module of claim 15 , wherein the alloy of copper includes at least one of iron or phosphorous.

17 . The half-bridge circuit power module of claim 13 , further comprising:

a fifth low-side transistor disposed on the first patterned metal layer and electrically coupled with the fifth patterned metal layer via a seventh conductive clip;

a sixth low-side transistor disposed on the second patterned metal layer and electrically coupled with the fifth patterned metal layer via the seventh conductive clip;

a fifth high-side transistor disposed on the third patterned metal layer and electrically coupled with the first patterned metal layer via an eighth conductive clip;

a sixth high-side transistor disposed on the fourth patterned metal layer and electrically coupled with the second patterned metal layer via a sixth conductive clip,

the first DC+ terminal being further electrically coupled with the third patterned metal layer via a fourth conductive post disposed between the second high-side transistor and the fifth high-side transistor on the third patterned metal layer;

the second DC+ terminal being further electrically coupled with the fourth patterned metal layer via a fifth conductive post disposed between the fourth high-side transistor and the sixth high-side transistor on the fourth patterned metal layer, and

the DC− terminal is further electrically coupled with the fifth patterned metal layer via a sixth conductive post disposed between the second conductive clip and the third conductive clip on the fifth patterned metal layer.

18 . A method for producing a half-bridge circuit power module, method comprising:

coupling a first high-side transistor and a second high-side transistor with a first patterned metal layer disposed on a surface of a substrate;

coupling a first low-side transistor and a second low-side transistors with a second patterned metal layer disposed on the surface of the substrate;

with a first conductive clip, electrically coupling the first high-side transistor with the second patterned metal layer;

with a second conductive clip, electrically coupling the second high-side transistor with the second patterned metal layer;

with a third conductive clip, electrically coupling the first low-side transistor with a third patterned metal layer disposed on the surface of the substrate;

with a fourth conductive clip, electrically coupling the second low-side transistor with the third patterned metal layer;

electrically coupling a DC+ terminal with the first patterned metal layer via a first conductive post disposed between the first high-side transistor and the second high-side transistor on the first patterned metal layer; and

electrically coupling a DC− terminal with the third patterned metal layer via a second conductive post disposed between the third conductive clip and the fourth conductive clip on the third patterned metal layer.

19 . The method of claim 18 , further comprising electrically coupling an output terminal with the second patterned metal layer via a third conductive post.

20 . The method of claim 19 , wherein the DC+ terminal is a first DC+ terminal, the method further comprising:

coupling a third high-side transistor with a fourth patterned metal layer disposed on the surface of the substrate;

coupling a fourth high-side transistor with the fourth patterned metal layer;

coupling a third low-side transistor with a fifth patterned metal layer on the surface of the substrate;

coupling a fourth low-side transistor with the fifth patterned metal layer;

with a fifth conductive clip, electrically coupling the third high-side transistor with the fifth patterned metal layer;

with a sixth conductive clip, electrically coupling the fourth high-side transistor with the fifth patterned metal layer; and

electrically coupling a second DC+ terminal with the fourth patterned metal layer via a fourth conductive post disposed between the third high-side transistor and the fourth high-side transistor on the fourth patterned metal layer; and

further electrically coupling the output terminal with the fifth patterned metal layer via fifth conductive post,

the third conductive clip further electrically coupling the third low-side transistor with the third patterned metal layer, and

the fourth conductive clip further electrically coupling the fourth low-side transistor with the third patterned metal layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2023
From: JEON, OSEOB; IM, SEUNGWON; THIRUKOLURI, RAJANI KUMAR; PAUL, ROVEENDRA
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 065862/0921 →
Continuity (6)
Continuation In Part 18154722 · Jan 13, 2023
Provisional Application 63481735 · Jan 26, 2023
Provisional Application 63383837 · Nov 15, 2022
Provisional Application 63380528 · Oct 21, 2022
Related Publication 20240138069A1 · Apr 25, 2024
Related Publication 20240237216A9 · Jul 11, 2024
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