MONOLITHIC STRUCTURE FOR SUBSTRATE BIASING FOR A TRANSISTOR THAT USES A TWO-DIMENSIONAL ELECTRON GAS
A monolithic implementation of an integrated circuit that includes a power transistor and a biasing circuit for biasing the substrate of the power transistor. For example, the integrated circuit comprises a semiconductor substrate; and an epitaxial stack epitaxially grown on the semiconductor substrate. A power transistor uses a portion of the epitaxial stack including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. Furthermore, a biasing circuit includes circuit elements that use a respective portion of the epitaxial stack including a respective portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. The biasing circuit is configured to bias a portion of the semiconductor substrate beneath the power transistor.
1 . An integrated circuit comprising:
a semiconductor substrate;
an epitaxial stack epitaxially grown on the semiconductor substrate, the epitaxial stack including a channel semiconductor layer and a barrier semiconductor layer epitaxially grown on the channel semiconductor layer; an interface between the channel semiconductor layer and the barrier semiconductor layer inducing a two-dimensional electron gas (2DEG) within the channel semiconductor layer;
a power transistor using a portion of the epitaxial stack including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer; and
a biasing circuit comprising a plurality of circuit elements, each of at least some of the plurality of circuit elements using a respective portion of the epitaxial stack including a respective portion of the channel semiconductor layer and a portion of the barrier semiconductor layer, the biasing circuit configured to bias a portion of the semiconductor substrate beneath the power transistor.
2 . The integrated circuit of claim 1 , the semiconductor substrate being a Silicon substrate.
3 . The integrated circuit of claim 1 , the barrier semiconductor layer being an AlGaN layer, the channel semiconductor layer being a GaN layer.
4 . The integrated circuit of claim 1 , the biasing circuit comprising:
a transistor, a drain of the transistor being connected to the substrate contact layer, a gate of the transistor being coupled to an inverter circuit, a source of the transistor being connected to ground.
5 . The integrated circuit of claim 1 , further comprising:
a source contact in conductive contact with the 2DEG;
a drain contact in conductive contact with the 2DEG;
a gate terminal that is proximate to the 2DEG such that voltages applied to the gate terminal control whether the 2DEG is continuous between the source contact and the drain contact; and
a substrate contact layer disposed immediately beneath the semiconductor substrate, the substrate contact layer being electrically disconnected from the source contact to allow for a different voltage to be applied to the substrate contact layer as compared to the source contact; the biasing circuit configured to bias the portion of the semiconductor substrate beneath the power transistor by applying a substrate bias voltage to the substrate contact layer.
6 . The integrated circuit of claim 5 , the biasing circuit being configured to bias the semiconductor substrate by applying a positive bias voltage to the substrate contact layer, the positive bias voltage being positive relative to a source voltage applied to the source terminal.
7 . The integrated circuit of claim 6 , the positive bias voltage being a fixed positive voltage relative to the source voltage.
8 . The integrated circuit of claim 6 , the positive bias voltage being selectively applied depending on a state of the transistor structure.
9 . The integrated circuit of claim 6 , the positive bias voltage changing depending on a state of the transistor structure.
10 . The integrated circuit of claim 6 , the biasing circuit being configured such that the positive bias voltage has a maximum voltage of more than 100 Volts to the semiconductor substrate.
11 . The integrated circuit of claim 5 , the biasing circuit further being configured to bias the substrate contact layer, the biasing circuit being connected to the substrate contact layer with a wire.
12 . The integrated circuit of claim 5 , the biasing circuit further being configured to bias the substrate contact layer, the biasing circuit being connected to the substrate contact layer with a via through a die through the integrated circuit to the substrate contact layer.
13 . The integrated circuit of claim 1 , the integrated circuit being encompassed within a package.
14 . The integrated circuit of claim 13 , the package being a PSOP package.
15 . The integrated circuit of claim 13 , the package being a TOLL package.
16 . The integrated circuit of claim 13 , the package being a PQFN package.
17 . An integrated circuit package comprising an integrated circuit that comprises:
a semiconductor substrate;
an epitaxial stack epitaxially grown on the semiconductor substrate, the epitaxial stack including a channel semiconductor layer and a barrier semiconductor layer epitaxially grown on the channel semiconductor layer; an interface between the channel semiconductor layer and the barrier semiconductor layer inducing a two-dimensional electron gas (2DEG) within the channel semiconductor layer;
a power transistor using a portion of the epitaxial stack including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer; and
a biasing circuit comprising a plurality of circuit elements, each of at least some of the plurality of circuit elements using a respective portion of the epitaxial stack including a respective portion of the channel semiconductor layer and a portion of the barrier semiconductor layer, the biasing circuit configured to bias a portion of the semiconductor substrate beneath the power.
18 . The integrated circuit package of claim 16 , the integrated circuit package being a PSOP package.
19 . The integrated circuit package of claim 16 , the integrated circuit package being a TOLL package.
20 . The integrated circuit package of claim 16 , the integrated circuit package being a PQFN package.