Granted Patent B2

US 12,633,923 · App. 18/496,179 · Granted May 19, 2026

Inventors: Thomas Pierre Georges Jouanneau (ST-Egreve, FR); Catherine Margaret Simone Marie Popon (Seyssins, FR); Mario Martino Zampogna (Catania, IT); Léa Sandrina Frédérique Enginger (Grenoble, FR)

Assignee: STMicroelectronics International N.V.

H03K19/018528G11C7/1057G11C7/12

Abstract

Claims (48)

1 . A level shifter circuit, comprising:

a first stage input circuit configured to receive an input voltage and generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage, and wherein the first stage input circuit comprises a plurality of low voltage threshold switches;

a first stage output circuit configured to receive the second voltage and to generate a third voltage, wherein the third voltage varies between the first low voltage and a second high voltage, and wherein the first stage output circuit comprises a first plurality of medium voltage switches;

a second stage input circuit configured to receive the third voltage and to generate a fourth voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage, and wherein the second stage input circuit comprises a second plurality of medium voltage switches, wherein the second low voltage is greater than the first low voltage;

a second stage output circuit configured to receive the fourth voltage and generate a fifth voltage, wherein the fifth voltage varies between the second low voltage and a third high voltage, and wherein the second stage output circuit comprises a third plurality of medium voltage switches; and

a buffering circuit configured to receive the fifth voltage and to generate an output voltage, wherein the output voltage varies between a third low voltage and the third high voltage.

2 . The level shifter circuit of claim 1 , wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage.

3 . The level shifter circuit of claim 1 , wherein the second low voltage is equal to the third low voltage.

4 . The level shifter circuit of claim 1 , wherein the first stage output circuit comprises a second plurality of low voltage switches.

5 . The level shifter circuit of claim 1 , wherein the first high voltage is greater than the first low voltage and is less than the third high voltage.

6 . The level shifter circuit of claim 1 , wherein the buffering circuit comprises a fourth plurality of medium voltage switches.

7 . The level shifter circuit of claim 1 , wherein each of the switches of the level shifter circuit is either a low voltage switch or a medium voltage switch.

8 . An array circuit, comprising:

an array of devices, wherein a plurality of devices of the array each comprise at least one high voltage switch;

a controller configured to generate a plurality of first control signals for controlling the array of devices; and

an array of level shifters, each level shifter configured to receive one of the first control signals from the controller as an input voltage, to generate one of a plurality of second control signals as an output voltage, and to provide the output voltage to one of the array of devices, wherein the level shifters each comprise:

a first stage input circuit configured to receive the input voltage and generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage, and wherein the first stage input circuit comprises a plurality of low voltage threshold switches,

a first stage output circuit configured to receive the second voltage and to generate a third voltage, wherein the third voltage varies between the first low voltage and a second high voltage, and wherein the first stage output circuit comprises a first plurality of medium voltage switches,

a second stage input circuit configured to receive the third voltage and to generate a fourth voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage, and wherein the second stage input circuit comprises a second plurality of medium voltage switches, wherein the second low voltage is greater than the first low voltage,

a second stage output circuit configured to receive the fourth voltage and generate a fifth voltage, wherein the fifth voltage varies between the second low voltage and a third high voltage, and wherein the second stage output circuit comprises a third plurality of medium voltage switches, and

a buffering circuit configured to receive the fifth voltage and to generate the output voltage, wherein the output voltage varies between a third low voltage and the third high voltage.

9 . The array circuit of claim 8 , wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage.

10 . The array circuit of claim 8 , wherein the second low voltage is equal to the third low voltage.

11 . The array circuit of claim 8 , wherein the first stage output circuit comprises a fourth plurality of low voltage switches.

12 . The array circuit of claim 8 , wherein the first high voltage is greater than the first low voltage and is less than the third high voltage.

13 . The array circuit of claim 8 , wherein the buffering circuit comprises a plurality of medium voltage switches.

14 . The array circuit of claim 8 , wherein each switch of each of the level shifters is either a low voltage switch or a medium voltage switch.

15 . A method of using a level shifter circuit, the method comprising:

with a first stage input circuit comprising a plurality of low voltage threshold switches:

receiving an input voltage, and

generating a second voltage based in part on the input voltage, wherein the second voltage varies between a first low voltage and a first high voltage;

with a first stage output circuit comprising a first plurality of medium voltage switches:

receiving the second voltage, and

generating a third voltage based in part on the second voltage, wherein the third voltage varies between the first low voltage and a second high voltage;

with a second stage input circuit comprising a second plurality of medium voltage switches:

receiving the third voltage, and

generating a fourth voltage based in part on the third voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage, wherein the second low voltage is greater than the first low voltage;

with a second stage output circuit comprising a third plurality of medium voltage switches:

receiving the fourth voltage, and

generating a fifth voltage based in part on the fourth voltage, wherein the fifth voltage varies between the second low voltage and a third high voltage; and

with a buffering circuit:

receiving the fifth voltage, and

generating an output voltage based in part on the fifth voltage, wherein the output voltage varies between a third low voltage and the third high voltage.

16 . The method of claim 15 , wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage.

17 . The method of claim 15 , wherein the second low voltage is equal to the third low voltage.

18 . The method of claim 15 , wherein the first stage output circuit comprises a plurality of low voltage switches.

19 . The method of claim 15 , wherein the first high voltage is greater than the first low voltage and is less than the third high voltage.

20 . The method of claim 15 , wherein each switch of the level shifter circuit is either a low voltage switch or a medium voltage switch.

Assignments (6)

Continuity (1)

References Cited (41)