Semiconductor structure and manufacturing method thereof
The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.
1. A method of manufacturing a semiconductor structure, comprising:
forming a first source/drain region;
forming a first dielectric layer above the first source/drain region;
removing a portion of the first dielectric layer;
forming a channel region along a sidewall of the first dielectric layer;
forming a gate region along a sidewall of the channel region;
forming a second dielectric layer above the first dielectric layer and the gate region;
removing a portion of the second dielectric layer to form an opening that exposes the channel region; and
forming a second source/drain region within the opening.
2. The method of claim 1 , wherein an upper surface of the first source/drain region is covered by the first dielectric layer after removing the portion of the first dielectric layer.
3. The method of claim 1 , wherein the channel region is also formed along a sidewall of the first source/drain region.
4. The method of claim 3 , wherein the channel region has a bottommost surface that is over a bottommost surface of the first source/drain region.
5. The method of claim 1 , wherein the channel region is laterally and directly between the gate region and the first source/drain region.
6. The method of claim 1 , wherein the opening within the second dielectric layer exposes an additional sidewall of the channel region.
7. The method of claim 1 , wherein the second source/drain region extends from below a topmost surface of the channel region to above the topmost surface of the channel region.
8. A method of manufacturing a semiconductor structure, comprising:
forming a first source/drain region over a substrate;
forming a first dielectric layer above the first source/drain region;
forming a channel layer along a sidewall of the first dielectric layer, wherein a first sidewall of the channel layer faces the first source/drain region;
forming a gate region along a second sidewall of the channel layer opposing the first sidewall; and
forming a second source/drain region along the first sidewall of the channel layer and vertically above the first source/drain region.
9. The method of claim 8 , wherein a bottom of the channel layer is vertically between a top and a bottom of the first source/drain region and wherein a top of the channel layer is vertically between a top and a bottom of the second source/drain region.
10. The method of claim 8 , further comprising:
forming a gate dielectric onto the second sidewall of the channel layer; and
forming the gate region onto the gate dielectric, so that the channel layer is laterally separated from the gate region by the gate dielectric.
11. The method of claim 8 , further comprising:
forming a third source/drain region over the substrate;
forming the first dielectric layer above the third source/drain region;
forming a second channel layer along a second sidewall of the first dielectric layer;
forming the gate region between the channel layer and the second channel layer; and
forming a fourth source/drain region along a sidewall of the second channel layer that faces away from the gate region.
12. The method of claim 11 , wherein the first source/drain region and the third source/drain region are substantially symmetric about a vertical line bisecting the gate region.
13. The method of claim 8 , wherein an outermost sidewall of the channel layer faces an outermost sidewall of the first source/drain region.
14. A semiconductor structure, comprising:
a conductive gate arranged over a lower dielectric layer;
a first source/drain disposed vertically above the lower dielectric layer;
a second source/drain disposed vertically above the first source/drain; and
a channel structure arranged laterally between the conductive gate and both the first source/drain and the second source/drain, wherein the channel structure vertically extends from along a side of the first source/drain to along a side of the second source/drain.
15. The semiconductor structure of claim 14 , further comprising:
a first dielectric layer vertically between the first source/drain and the second source/drain, wherein the channel structure extends along a side of the first dielectric layer.
16. The semiconductor structure of claim 14 , wherein an entirety of the channel structure is laterally outside of the first source/drain.
17. The semiconductor structure of claim 14 , wherein the channel structure has a bottommost surface that is vertically between a bottommost surface of the first source/drain and a topmost surface of the first source/drain.
18. The semiconductor structure of claim 14 , wherein the channel structure vertically overlaps a part, but not all, of the first source/drain.
19. The semiconductor structure of claim 14 , wherein the channel structure has a larger height than either the first source/drain or the second source/drain.
20. The semiconductor structure of claim 14 , further comprising:
a gate dielectric layer laterally between the conductive gate and the channel structure, wherein both the gate dielectric layer and the channel structure vertically extend between a topmost surface of the conductive gate and a bottommost surface of the conductive gate.