Storage controller and operating method of the storage controller
A storage controller includes a host interface configured to communicate with a host, a buffer memory configured to buffer data read from a non-volatile memory, a cache memory including a plurality of cache lines and configured to store the data in at least one of the plurality of cache lines, and a cache controller configured to manage a status bitmap. The status bitmap indicates priority information of the plurality of cache lines according to an operation corresponding to a request received from the host interface, and the cache controller is further configured to select a victim cache line, among the plurality of cache lines, to be replaced based on the status bitmap. In this case, the operation corresponding to the request corresponds to one of normal read, prefetch, read-after-read, and read-after-prefetch.
1 . A storage controller comprising:
a host interface configured to communicate with a host;
a buffer memory configured to buffer data read from a non-volatile memory;
a cache memory including a plurality of cache lines and configured to store the data in at least one of the plurality of cache lines; and
a cache controller configured to manage a status bitmap, the status bitmap indicating priority information of the plurality of cache lines according to an operation corresponding to a request received from the host interface, and the cache controller further configured to select a victim cache line, among the plurality of cache lines, to be replaced based on the status bitmap,
wherein the cache controller is further configured to set a priority of a cache line differently depending on whether the operation corresponds to a normal read, a prefetch, a read-after-read, or a read-after-prefetch, the read-after-prefetch being a case in which data corresponding to a read request received from the host corresponds to data prefetched by a prefetch request previously issued from the host interface, and
wherein the cache controller is further configured to set a priority of a first cache line corresponding to the prefetch or the read-after-read higher than a priority of a second cache line corresponding to the normal read or the read-after-prefetch, such that the second cache line is selected as the victim cache line prior to the first cache line.
2 . The storage controller of claim 1 , wherein the status bitmap includes a promotion bitmap for setting the priority,
the promotion bitmap includes a plurality of promotion bits corresponding to the plurality of cache lines, and
the cache controller is further configured to select the victim cache line based on the plurality of promotion bits.
3 . The storage controller of claim 2 , wherein the cache controller is further configured to
set a first promotion bit of the plurality of promotion bits corresponding to the first cache line having a high reusability among the plurality of cache lines, to 1, and
clear a second promotion bit of the plurality of promotion bits corresponding to the second cache line having a lower reusability than that of the first cache line among the plurality of cache lines, to 0.
4 . The storage controller of claim 2 , wherein the cache controller is further configured to
set a promotion bit of the plurality of promotion bits to 1 in response to the operation corresponding to the prefetch or the read-after-read, and
clear the promotion bit to 0 in response to the operation corresponding to the read-after-prefetch.
5 . The storage controller of claim 2 , wherein the status bitmap further includes a prefetch bitmap for indicating whether there is the prefetch,
the prefetch bitmap comprises a plurality of prefetch bits corresponding to the plurality of cache lines, and
the cache controller is further configured to set a prefetch bit to 1 when the operation corresponds to the prefetch.
6 . The storage controller of claim 2 , wherein the status bitmap further includes a valid bitmap,
the valid bitmap comprises a plurality of valid bits corresponding to the plurality of cache lines, and
the cache controller is further configured to set a valid bit to 1 in response to the operation corresponding to the normal read or the prefetch.
7 . The storage controller of claim 2 , wherein the status bitmap further comprises a done bitmap,
the done bitmap comprises a plurality of done bits corresponding to the plurality of cache lines, and
the cache controller is further configured to
set a done bit to 1 in response to data transmission to the host being completed by the normal read, the read-after-read, or the read-after-prefetch, and
set the done bit to 1 in response to data loading to the buffer memory being completed by the prefetch.
8 . The storage controller of claim 2 , wherein the cache controller comprises:
a victim condition composition unit configured to reconfigure the status bitmap according to the operation;
a victim cache line selection unit configured to select, as the victim cache line, a cache line having a low priority among the plurality of cache lines according to the status bitmap; and
a downgrade unit configured to downgrade one or more promotion bits included in the status bitmap, to 0.
9 . The storage controller of claim 8 , wherein the victim condition composition unit is further configured to
reconfigure the status bitmap in response to the operation corresponding to the normal read or the prefetch to determine a reconfigured status bitmap, and
calculate victim candidates selectable as the victim cache line from the reconfigured status bitmap.
10 . The storage controller of claim 8 , wherein the status bitmap comprises a promotion bit and a done bit corresponding to each of the plurality of cache lines, and
the victim condition composition unit is further configured to output a victim condition value from a result of calculating the promotion bit and the done bit.
11 . The storage controller of claim 10 , wherein the victim condition value is generated from an AND operation applied to the done bit and the result of a NOT operation applied to the promotion bit.
12 . The storage controller of claim 10 , wherein
the victim cache line selection unit is further configured to search for victim condition values corresponding to the plurality of cache lines, and
the victim cache line selection unit is further configured to start from a current pointer, and select a new victim cache line that first satisfies a victim condition after the current pointer.
13 . The storage controller of claim 12 , wherein the victim cache line selection unit is further configured to
update the current pointer to a previous pointer, and
update an index of the victim cache line to a new current pointer.
14 . The storage controller of claim 13 , wherein the downgrade unit is further configured to downgrade promotion bits between the previous pointer and the new current pointer, to 0.
15 . The storage controller of claim 2 , wherein the cache controller is further configured to
in response to the cache controller receiving a request from the host, determine whether a cache hit has occurred,
in response to determining that a cache hit has occurred, determine whether an operation corresponding to the request corresponds to the read-after-read;
in response to determining that the operation corresponding to the request corresponds to the read-after-read, set a promotion bit of the plurality of promotion bits to 1, and
in response to determining that the operation corresponding to the request is a read-after-prefetch, clear the promotion bit to 0.
16 . A storage device comprising:
a non-volatile memory; and
a storage controller configured to control the non-volatile memory,
wherein the storage controller includes,
a host interface configured to communicate with a host;
a buffer memory configured to buffer data read from the non-volatile memory;
a cache memory including a plurality of cache lines and configured to store the data in at least one of the plurality of cache lines; and
a cache controller configured to manage a status bitmap, the status bitmap indicating priority information of the plurality of cache lines according to an operation corresponding to a request received from the host interface, and the cache controller further configured to select a victim cache line, among the plurality of cache lines, to be replaced based on the status bitmap,
wherein the cache controller is further configured to set a priority of a cache line differently depending on whether the operation corresponds to a normal read, a prefetch, a read-after-read, or a read-after-prefetch, the read-after-prefetch being a case in which data corresponding to a read request received from the host corresponds to data prefetched by a prefetch request previously issued from the host interface, and
wherein the cache controller is further configured to set a priority of a first cache line corresponding to the prefetch or the read-after-read higher than a priority of a second cache line corresponding to the normal read or the read-after-prefetch, such that the second cache line is selected as the victim cache line prior to the first cache line.