IP Library › Granted Patent US 12,587,110
Granted Patent B2
US 12,587,110 · App. 18/506,792 · Granted Mar 24, 2026

Quasi three-level power converter

Inventors: Peng Shuai (Shenzhen, CN); Chengmin Li (Lausanne, CH); Drazen Dujic (Lausanne, CH)
Assignee: Huawei Technologies Co., Ltd.
H02M7/4835H02M1/0029H02M1/0095H02M7/487H02M7/5395
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Quick Facts
Patent No.
US 12,587,110
App. No.
18/506,792
Granted
Mar 24, 2026
Kind
B2
Abstract

The present disclosure provides a power converter, comprising: a positive terminal, a neutral terminal, a negative terminal, a first intermediate node, a second intermediate node, and an AC terminal. Vertical and horizontal switches are configured to switch a DC voltage between the positive and negative terminal to an AC voltage at the AC terminal. The AC voltage comprises three main voltage levels. A transition between any two of the main voltage levels follow a trapezoidal shape with at least one voltage sub-level.

Claims (54)

1 . A power converter, comprising:

a positive terminal;

a neutral terminal;

a negative terminal, wherein a first DC link capacitor connects the positive terminal with the neutral terminal and a second DC link capacitor connects the neutral terminal with the negative terminal;

a first intermediate node, wherein a first vertical switch connects the positive terminal with the first intermediate node and a second vertical switch connects the first intermediate node with the neutral terminal;

a second intermediate node, wherein a third vertical switch connects the neutral terminal with the second intermediate node and a fourth vertical switch connects the second intermediate node with the negative terminal; and

an AC terminal, wherein a first horizontal switch connects the first intermediate node with the AC terminal and a second horizontal switch connects the second intermediate node with the AC terminal,

wherein the vertical and horizontal switches are configured to switch a DC voltage between the positive and negative terminal to an AC voltage at the AC terminal, the AC voltage comprising three main voltage levels, a transition between any two of the main voltage levels following a trapezoidal shape with at least one voltage sub-level, wherein each of the vertical switches are made of directly series-connected power semiconductor devices.

2 . The power converter of claim 1 ,

wherein the vertical switches are configured to switch based on a modulation waveform at a fundamental frequency, wherein the fundamental frequency is 50/3 Hz, 50 Hz or 60 Hz; and

wherein the horizontal switches are configured to switch based on a carrier waveform at a carrier frequency, wherein the carrier waveform is a triangular carrier waveform.

3 . The power converter of claim 2 ,

wherein a switching signal for the horizontal switches is based on a comparison between the carrier waveform and the modulation waveform.

4 . The power converter of claim 2 ,

wherein the vertical and horizontal switches are configured to switch based on a space vector modulation, and wherein one phase leg comprises:

a first switching state (P) in which the AC voltage at the AC terminal equals to a positive voltage at the positive terminal;

a second switching state (N) in which the AC voltage at the AC terminal equals to a negative voltage at the negative terminal;

a third switching state (L) in which the AC voltage at the AC terminal equals to a zero voltage switched from the neutral terminal via the second horizontal switch to the AC terminal; and

a fourth switching state (U) in which the AC voltage at the AC terminal equals to a zero voltage switched from the neutral terminal via the first horizontal switch to the AC terminal.

5 . The power converter of claim 4 , wherein the horizontal switches are configured to enable:

during a positive cycle of the modulation waveform, only a transition between the first switching state (P) and the third switching state (L);

during a zero crossing point of the modulation waveform, only a transition between the third switching state (L) and the fourth switching state (U); and

during a negative cycle of the modulation waveform, only a transition between the second switching state (N) and the fourth switching state (U).

6 . The power converter of claim 2 ,

wherein each of the horizontal switches comprises at least two switching cells, each of the at least two switching cells of the respective horizontal switch being configured to output a zero and at least a positive voltage.

7 . The power converter of claim 3 ,

wherein each of the horizontal switches comprises at least two switching cells, each of the at least two switching cells of the respective horizontal switch being configured to output a zero and at least a positive voltage.

8 . The power converter of claim 4 ,

wherein each of the horizontal switches comprises at least two switching cells, each of the at least two switching cells of the respective horizontal switch being configured to output a zero and at least a positive voltage.

9 . The power converter of claim 5 ,

wherein each of the horizontal switches comprises at least two switching cells, each of the at least two switching cells of the respective horizontal switch being configured to output a zero and at least a positive voltage.

10 . The power converter of claim 6 ,

wherein the at least two switching cells of the first horizontal switch are arranged in series between the first intermediate node and the AC terminal; and

wherein the at least two switching cells of the second horizontal switch are arranged in series between the second intermediate node and the AC terminal.

11 . The power converter of claim 10 ,

wherein two successive switching cells of the series of the at least two switching cells are configured to switch with a mutual time delay corresponding to a dwell time.

12 . The power converter of claim 11 ,

wherein the switching cells are configured to shape the transition between any two of the main voltage levels of the power converter based on the dwell time.

13 . The power converter of claim 11 ,

wherein the dwell time is the same or is different for two switching cells of the series of the at least two switching cells.

14 . The power converter of claim 12 ,

wherein a branch controller is configured to adjust the dwell time for each switching cell based on a balance of voltages among capacitors in the respective switching cell.

15 . The power converter of claim 11 , further comprising:

a branch controller configured to provide the switching signal and adjust the dwell time for each switching cell.

16 . The power converter of claim 15 ,

wherein the branch controller is configured to adjust the dwell time for each switching cell based on a balance of voltages among capacitors in the switching cell.

17 . The power converter of claim 6 ,

wherein each of the at least two switching cells comprises at least one main switch, at least one auxiliary switch, and a switching cell capacitor.

18 . The power converter of claim 17 ,

wherein each of the at least two switching cells further comprises a resistor arranged in series with the switching cell capacitor.

19 . The power converter of claim 17 ,

wherein each of the at least two switching cells further comprises a resistor arranged in parallel with the switching cell capacitor.

20 . The power converter of claim 1 , further comprising:

a central controller configured to provide switching signals, wherein the switching signals comprise pulse width modulation, for switching the vertical switches and the horizontal switches.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2024
From: SHUAI, PENG; LI, CHENGMIN; DUJIC, DRAZEN
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 066860/0042 →
Continuity (2)
Continuation PCTEP2021062659 · May 12, 2021
Related Publication 20240079966A1 · Mar 7, 2024
References Cited (20)
US 9641098B2 · Fu · 2017 [cited by examiner]
US 20140254228A1 · Ying et al. · 2014 [cited by applicant]
US 20170257022A1 · Bryant · 2017 [cited by applicant]
US 20190115840A1 · Li et al. · 2019 [cited by applicant]
US 20250015717A1 · Zeng · 2025 [cited by examiner]
CA 2827664A1 · 2014 [cited by applicant]
CN 112152464A · 2020 [cited by applicant]
SE 1951506A1 · 2020 [cited by applicant]
WO 2017021169A1 · 2017 [cited by applicant]
WO 2019238443A1 · 2019 [cited by applicant]
Adam et al., “Review of dc-dc converters for multi-terminal HVDC transmission networks”, IET Power Electronics, vol. 9, No. 2, pp. 281-296 (Feb. 10, 2016). [cited by applicant]
Bertoldi et al., “Quasi-Two-Level converter operation strategy for overvoltage mitigation in long cable applications”, IEEE International Electric Machines & Drives Conference (IEMDC), pp. 1621-1627 (May 12, 2019). [cited by applicant]
Gowaid et al., “Analysis and Design of a Modular Multilevel Converter with Trapezoidal Modulation for Medium and High Voltage DC-DC Transformers”, IEEE Transactions on Power Electronics, vol. 30, No. 10, total 19 pages … [cited by applicant]
Mertens et al., “Quasi Two-Level PWM Operation of an MMC Phase Leg with Reduced Module Capacitance,” IEEE Transactions on Power Electronics, vol. 31, No. 10, Total 5 pages (Oct. 2016). [cited by applicant]
Gowaid et al., “Quasi two-level operation of modular multilevel converter for use in a high-power DC transformer with DC fault isolation capability,” IEEE Transactions on Power Electronics, vol. 30, No. 1, Total 17 page… [cited by applicant]
Milovanovic et al., “Comprehensive Analysis and Design of a Quasi Two-Level Converter Leg,” CPSS Transactions on Power Electronics and Applications, vol. 4 No. 3, Total 17 pages (Sep. 2019). [cited by applicant]
Li et al., “Space Vector Modulation for SiC and Si Hybrid ANPC Converter in Medium-Voltage High-Speed Drive System,” IEEE Transactions on Power Electronics, vol. 35, No. 4, Total 12 pages (Apr. 2020). [cited by applicant]
Adam et al., “Capacitor balance issues of the diode-clamped multilevel inverter operated in a quasi two-state mode,” IEEE Transactions on Industrial Electronics, vol. 55, No. 8, Total 12 pages (Aug. 2008). [cited by applicant]
Sinha Akanksha et al., “An inclusive review on different multilevel inverter topologies, their modulation and control strategies for a grid connected photo-voltaic system,” Solar Energy, Elsevier, Amsterdam, NL, vol. 17… [cited by applicant]
Naderi Roozbeh et al., “Dual Flying Capacitor Active-NeutralPoint-Clamped Multilevel Converter,” IEEE Transactions On Power Electronics, Institute of Electrical and Electronics Engineers, USA, vol. 31, No. 9, Total 9 pa… [cited by applicant]