ACHIEVING DIFFERENT HIGH VOLTAGES ON INDIVIDUAL BITLINES OF A MEMORY DEVICE
Embodiments disclosed herein are directed to a memory device, comprising a set of storage elements, a set of bitlines, where each bitline of the set of bitlines is associated with a respective storage element of the set of storage elements, and one or more control circuits. The one or more control circuits configured to during a memory operation performed on the set of storage elements: charge the set of bitlines to a high voltage level; in response to the set of bitlines reaching the high voltage level, float the set of bitlines; and discharge bitlines of the set of bitlines that are associated with selected storage elements of the set of storage elements.
1 . A storage system, comprising:
a set of storage elements;
a set of bitlines, each bitline of the set of bitlines being associated with a respective storage element of the set of storage elements; and
one or more control circuits, the one or more control circuits configured to during a memory operation performed on the set of storage elements:
charge the set of bitlines to a high voltage level; and
discharge bitlines of the set of bitlines that are associated with selected storage elements of the set of storage elements.
2 . The storage system of claim 1 , wherein the one or more control circuits is further configured to:
in response to the set of bitlines reaching the high voltage level, float the set of bitlines.
3 . The storage system of claim 1 , wherein the one or more control circuits is further configured to:
select a voltage source associated with the high voltage level.
4 . The storage system of claim 1 , further comprising:
a set of sense circuits, each sense circuit of the set of sense circuits being connected to a respective bitline of the set of bitlines and including:
a first transistor configured to isolate a sense circuit from the high voltage level; and
a second transistor configured to discharge the high voltage level from a bitline.
5 . The storage system of claim 3 , wherein the one or more control circuits is further configured to:
apply different voltages to gates of second transistors of sense circuits associated with the selected storage elements.
6 . The storage system of claim 3 , wherein the one or more control circuits is further configured to:
apply different pulse widths to gates of second transistors of sense circuits associated with the selected storage elements.
7 . The storage system of claim 1 , wherein the one or more control circuits is further configured to:
discharge the bitlines that are associated with the selected storage elements for a predetermined discharge period.
8 . A method of operating a non-volatile semiconductor memory device, the method comprising:
charging a set of bitlines to a high voltage level, each bitline of the set of bitlines being associated with a respective storage element of a set of storage elements; and
discharging bitlines of the set of bitlines that are associated with selected storage elements of the set of storage elements.
9 . The method of claim 8 , further comprising:
in response to the set of bitlines reaching the high voltage level, floating the set of bitlines.
10 . The method of claim 8 , further comprising:
selecting a voltage source associated with the high voltage level.
11 . The method of claim 8 , further comprising:
applying different voltages to gates of transistors of sense circuits associated with the selected storage elements, wherein the transistors are configured to discharge the high voltage level from a bitline.
12 . The method of claim 8 , further comprising:
applying different pulse widths to gates of transistors of sense circuits associated with the selected storage elements, wherein the transistors are configured to discharge the high voltage level from a bitline.
13 . The method of claim 8 , further comprising:
discharging the bitlines that are associated with the selected storage elements for a predetermined discharge period.
14 . An apparatus, comprising:
a set of storage elements;
a set of bitlines, each bitline of the set of bitlines being associated with a respective storage element of the set of storage elements; and
a means for performing a memory operation on the set of storage elements, the means for performing the memory operation on the set of storage elements being configured to:
charge the set of bitlines to a high voltage level; and
discharge bitlines of the set of bitlines that are associated with selected storage elements of the set of storage elements.
15 . The apparatus of claim 14 , the means for performing the memory operation on the set of storage elements being further configured to:
in response to the set of bitlines reaching the high voltage level, float the set of bitlines.
16 . The apparatus of claim 15 , the means for performing the memory operation on the set of storage elements being further configured to:
select a voltage source associated with the high voltage level.
17 . The apparatus of claim 14 , further comprising:
a set of sense circuits, each sense circuit of the set of sense circuits being connected to a respective bitline of the set of bitlines and including:
a first transistor configured to isolate a sense circuit from the high voltage level; and
a second transistor configured to discharge the high voltage level from a bitline.
18 . The apparatus of claim 17 , the means for performing the memory operation on the set of storage elements being further configured to:
apply different voltages to gates of second transistors of sense circuits associated with the selected storage elements.
19 . The apparatus of claim 17 , the means for performing the memory operation on the set of storage elements being further configured to:
apply different pulse widths to gates of second transistors of sense circuits associated with the selected storage elements.
20 . The apparatus of claim 14 , the means for performing the memory operation on the set of storage elements being further configured to:
discharge the bitlines that are associated with the selected storage elements for a predetermined discharge period.