Two-stage emergency data storing operation
Implementations described herein relate to a two-stage emergency data storing operation. In some implementations, a memory device may detect a power loss notification signal that indicates a power loss condition of the memory device. The memory device may read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage. The first data storing stage may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss. The memory device may initiate the data storing operation and may selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage.
1. A memory device, comprising:
one or more components configured to:
detect a power loss notification signal that indicates a power loss condition of the memory device;
read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage,
wherein the first data storing stage includes storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage includes storing data and metadata associated with the memory device prior to the memory device experiencing the power loss;
initiate the data storing operation; and
selectively acknowledge the power loss condition based on completing the first data storing stage and the second data storing stage.
2. The memory device of claim 1 , wherein the first data storing stage includes an emergency power fail operation and the second data storing stage includes a forced quiescence operation.
3. The memory device of claim 1 , wherein a first state of the mode register bit indicates for the memory device to perform the data storing operation that includes the first data storing stage and the second data storing stage, and a second state of the mode register bit indicates for the memory device to perform a data storing operation that includes only the first data storing stage.
4. The memory device of claim 1 , wherein the one or more components, to detect the power loss notification signal, are configured to receive the power loss notification signal from a power management component.
5. The memory device of claim 1 , wherein the one or more components, to selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage, are configured to transmit a power loss acknowledgement signal to a power management component based on completing the first data storing stage and the second data storing stage.
6. The memory device of claim 1 , wherein the one or more components, to selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage, are configured not to transmit a power loss acknowledgement signal to a power management component based on completing the first data storing stage but not completing the second data storing stage.
7. The memory device of claim 1 , wherein the one or more components are configured to perform the data storing operation using power received from one or more capacitors associated with the memory device.
8. The memory device of claim 1 , wherein the one or more components, to initiate the data storing operation, are configured to:
initiate the first data storing stage based on detecting the power loss notification signal;
complete the first data storing stage prior to a time associated with the first data storing stage; and
initiate the second data storing stage based on completing the first data storing stage prior to the time associated with the second data storing stage.
9. A system, comprising:
a power management component configured to:
detect a power loss condition associated with a memory device; and
transmit a power loss notification signal to the memory device that indicates the power loss condition; and
the memory device, wherein the memory device is configured to:
receive the power loss notification signal;
read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage,
wherein the first data storing stage includes storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage includes storing data and metadata associated with the memory device prior to the memory device experiencing the power loss;
initiate the data storing operation; and
selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage.
10. The system of claim 9 , wherein the first data storing stage includes an emergency power fail operation and the second data storing stage includes a forced quiescence operation.
11. The system of claim 9 , wherein a first state of the mode register bit indicates for the memory device to perform the data storing operation that includes the first data storing stage and the second data storing stage, and a second state of the mode register bit indicates for the memory device to perform another data storing operation that includes only the first data storing stage.
12. The system of claim 9 , wherein the memory device, to selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage, is configured to transmit a power loss acknowledgement signal to the power management component based on completing the first data storing stage and the second data storing stage.
13. The system of claim 9 , wherein the memory device, to selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage, is configured not to transmit a power loss acknowledgement signal to the power management component based on completing the first data storing stage but not completing the second data storing stage.
14. The system of claim 9 , wherein the memory device is configured to perform the data storing operation using power received from one or more capacitors associated with the memory device.
15. A method performed by a memory device, comprising:
reading a mode register bit that indicates to perform a data storing operation that includes an emergency power fail operation and a forced quiescence operation;
initiating and completing the emergency power fail operation;
initiating the forced quiescence operation based on completing the emergency power fail operation; and
asserting a power loss acknowledgement based on completing the forced quiescence operation.
16. The method of claim 15 , further comprising detecting a power loss condition or a standard shut-down condition of the memory device, wherein reading the mode register bit comprises reading the mode register bit based on detecting the power loss condition or the standard shut-down condition of the memory device.
17. The method of claim 15 , wherein a first state of the mode register bit indicates for the memory device to perform the data storing operation that includes the emergency power fail operation and the forced quiescence operation, and a second state of the mode register bit indicates for the memory device to perform a data storing operation that includes only one of the emergency power fail operation or the forced quiescence operation.
18. The method of claim 15 , wherein initiating and completing the emergency power fail operation, and initiating the forced quiescence operation, comprises initiating and completing the emergency power fail operation, and initiating the forced quiescence operation, using power received from one or more capacitors associated with the memory device.
19. The method of claim 15 , wherein asserting the power loss acknowledgement comprises transmitting a power loss acknowledgement signal to a power management component based on completing the emergency power fail operation and the forced quiescence operation.
20. The method of claim 15 , further comprising performing a controller level reset or de-asserting a power loss notification signal based on completing the emergency power fail operation and the forced quiescence operation.