Methods and systems for implementing stream data updates
In accordance with some embodiments of the present disclosure, a method is performed on a memory storage device for updating data stored in the memory storage device. The method includes writing a first stream data to a first portion of memory, wherein the first stream data includes a plurality of substreams, and writing first additional data to a second portion of memory, wherein the first additional data includes data indicative of an update of at least one substream of the first stream data and is no larger than a substream of the plurality of substreams of the first stream data. Concurrent with writing the first additional data, the method also includes writing second additional data to the second portion of memory, wherein the second additional data includes at least one of data indicative of an update of at least one substream of a second stream data, or non-stream data.
1 . A method performed on a memory storage device for updating data stored in the memory storage device, the method comprising:
writing a first stream data to a first portion of memory, wherein the first stream data comprises a plurality of substreams;
writing first additional data to a second portion of memory, wherein the first additional data:
comprises data indicative of an update of at least one substream of the first stream data, and
is no larger than a substream of the plurality of substreams of the first stream data; and
concurrent with writing the first additional data, writing second additional data to the second portion of memory, wherein the second additional data comprises data indicative of an update of at least one substream of a second stream data, wherein the second stream data is different than the first stream data, and non-stream data.
2 . The method of claim 1 , wherein the first additional data is smaller than every respective substream of the plurality of substreams of the first stream data.
3 . The method of claim 1 , further comprising:
reading the first and second portions of memory; and
reconciling the first stream data and the first additional data based on one or more stream IDs or logical block addresses associated with the first stream data and the first additional data, without modifying the second additional data stored in the second portion of memory.
4 . The method of claim 1 , wherein the second additional data comprises data indicative of an update of at least one substream of a second stream data, the method further comprising:
writing the second stream data to a third portion of memory.
5 . The method of claim 4 , wherein the second additional data is no larger than a substream of a plurality of substreams of the second stream data.
6 . The method of claim 5 , further comprising:
reading the second and third portions of memory; and
reconciling the second stream data and the second additional data based on one or more stream IDs or logical block addresses associated with the second stream data and the second additional data, without modifying the first additional data stored in the second portion of memory.
7 . The method of claim 1 , further comprising performing the method of claim 1 in response to receiving one or more commands from a host device.
8 . The method of claim 1 , wherein each of the first portion of memory and the second portion of memory is an individually addressable erase unit.
9 . A system comprising:
a storage device, the storage device comprising memory and processing circuitry, wherein the processing circuitry is configured to:
write a first stream data to a first portion of the memory, wherein the first stream data comprises a plurality of substreams;
write first additional data to a second portion of the memory, wherein the first additional data:
comprises data indicative of an update of at least one substream of the first stream data, and
is no larger than a substream of the plurality of substreams of the first stream data; and
concurrent with writing the first additional data, write second additional data to the second portion of the memory, wherein the second additional data comprises data indicative of an update of at least one substream of a second stream data, wherein the second stream data is different than the first stream data, and non-stream data.
10 . The system of claim 9 , wherein the processing circuitry is further configured to write first additional data that is smaller than every respective substream of the plurality of substreams of the first stream data.
11 . The system of claim 9 , wherein the processing circuitry is further configured to:
read the first and second portions of the memory; and
reconcile the first stream data and the first additional data based on one or more stream IDs or logical block addresses associated with the first stream data and the first additional data, without modifying the second additional data stored in the second portion of the memory.
12 . The system of claim 9 , wherein the second additional data comprises data indicative of an update of at least one substream of a second data stream, wherein the processing circuitry is further configured to:
write the second stream data to a third portion of the memory.
13 . The system of claim 12 , wherein the processing circuitry is further configured to write second additional data that is no larger than a substream of a plurality of substreams of the second stream data.
14 . The system of claim 13 , wherein the processing circuitry is further configured to:
read the second and third portions of the memory; and
reconcile the second stream data and the second additional data based on one or more stream IDs or logical block addresses associated with the second stream data and the second additional data, without modifying the first additional data stored in the second portion of the memory.
15 . The system of claim 9 , further comprising a host device, wherein the processing circuitry is further configured to:
receive one or more commands from the host device; and
write at least one of the first stream data, the first additional data, or the second additional data in response to receiving the one or more commands.
16 . The system of claim 9 , wherein each of the first portion of memory and the second portion of memory is an individually addressable erase unit.
17 . A non-transitory computer-readable medium having non-transitory computer-readable instructions encoded thereon that, when executed by processing circuitry, cause the processing circuitry to:
write a first stream data to a first portion of memory, wherein the first stream data comprises a plurality of substreams;
write first additional data to a second portion of memory, wherein the first additional data:
comprises data indicative of an update of at least one substream of the first stream data, and
is no larger than a substream of the plurality of substreams of the first stream data; and
concurrent with writing the first additional data, write second additional data to the second portion of memory, wherein the second additional data comprises data indicative of an update of at least one substream of a second stream data, wherein the second stream data is different than the first stream data, and non-stream data.
18 . The non-transitory computer-readable medium of claim 17 , wherein the instructions further cause the processing circuitry to write first additional data that is smaller than every respective substream of the plurality of substreams of the first stream data.
19 . The non-transitory computer-readable medium of claim 17 , wherein the instructions further cause the processing circuitry to:
read the first and second portions of memory; and
reconcile the first stream data and the first additional data based on one or more stream IDs or logical block addresses associated with the first stream data and the first additional data, without modifying the second additional data stored in the second portion of memory.
20 . The non-transitory computer-readable medium of claim 17 , wherein the second additional data comprises data indicative of an update of at least one substream of a second stream data, wherein the instructions further cause the processing circuitry to:
write the second stream data to a third portion of memory, wherein the second additional data is smaller than every respective substream of the plurality of substreams of the second stream data.