Protection of an integrated circuit against electrostatic discharges
An ESD protection circuit includes a first voltage limiter having a first input terminal electrically coupled to each first signal pad of an integrated circuit by a first diode mounted in reverse bias during the integrated circuit operation. The first voltage limiter is mounted to be conductive between each first signal pad and ground during a positive ESD on the first signal pad. A second voltage limiter is electrically coupled and mounted to be conductive in the same direction as the first voltage limiter, between an external power supply pad and ground. An internal node outputs an internal power supply voltage to the domain, and is passed through by a current in response to a positive ESD on the power supply pad which is lower than the current passing through the first voltage limiter. A blocking diode is electrically connected between the first input terminal and the power supply pad.
1 . An integrated circuit, comprising:
several first signal input and/or output pads, wherein a domain of the integrated circuit is coupled to said first signal input and/or output pads;
at least one second pad configured to receive a first respective power supply voltage;
at least one third pad configured to be coupled to a cold feed point; and
a circuit for protecting said domain against electrostatic discharge including:
a first voltage limiting module having a first input terminal which is electrically coupled to each first signal input and/or output pad by a first diode mounted so as to be reverse biased during the operation of the integrated circuit;
wherein the first voltage limiting module is configured to be mounted to be conductive between each first signal input and/or output pad and said at least one third pad during a positive electrostatic discharge on one of the first signal input and/or output pads;
at least one second voltage limiting circuit electrically coupled between said at least one second pad and said at least one third pad;
wherein each second voltage limiting circuit is configured to be mounted to be conductive between the corresponding at least one second pad and the corresponding at least one third pad during a positive electrostatic discharge on the at least one second pad, the second voltage limiting circuit having an internal node configured to output a second power supply voltage to said domain, and configured, in the presence of a positive electrostatic discharge on the corresponding at least one second pad, to be passed through by a current which is lower than the current passing through the first voltage limiting module; and
a second diode which is electrically connected between said first input terminal and said at least one second pad so as to be forward-biased between said at least one second pad and the first input terminal of the first voltage limiting module during a positive discharge on the corresponding at least one second pad.
2 . The integrated circuit according to claim 1 , wherein the protection circuit comprises:
first pairs of first diodes which are connected in parallel and respectively associated with the first signal input and/or output pads, each first pair including two first diodes connected in series in a same direction, a common terminal of the two first diodes being coupled to the corresponding first signal input and/or output pad;
wherein the first voltage limiting module is connected in parallel with the first pairs of diodes;
a second pair of second diodes connected in parallel with the first voltage limiting circuit module, the second pair including two second diodes connected in series in a same direction as the first diodes, a common terminal of the two second diodes being electrically coupled to said at least one second pad;
wherein each second voltage limiting circuit includes a second voltage limiting module connected in series with a resistive element, a common terminal between the resistive element and the second voltage limiting module forming a second input terminal for the second voltage limiting module as well as said internal node;
wherein anodes of all diodes having their cathode connected either to one of the first signal input and/or output pads or to said at least one second pad are electrically coupled to said at least one third pad.
3 . The integrated circuit according to claim 2 , wherein the circuit for protecting comprises:
a first discharge rail coupled to said input terminal of the first voltage limiting module and to cathodes of all diodes having their anode coupled either to one of the first signal input and/or output pads or to the at least one second pad; and
a second discharge rail coupled to the at least one third pad and to the anodes of all diodes having their cathode connected either to one of the first signal input and/or output pads or to said at least one second pad.
4 . The integrated circuit according to claim 2 , wherein the first voltage limiting module and said at least one second voltage limiting module have a similar structure.
5 . The integrated circuit according to claim 4 :
wherein the first voltage limiting module includes at least one first lateral bipolar transistor having a collector forming said first input terminal, an emitter coupled to the corresponding at least one third pad and a base connected to the corresponding at least one third pad by a first base resistor; and
wherein each second voltage limiting module includes at least one second lateral bipolar transistor having a collector forming said second input terminal, an emitter coupled to the corresponding at least one third pad and a base connected to the corresponding at least one third pad by a second base resistor.
6 . The integrated circuit according to claim 5 , wherein said at least one second voltage limiting module has a space requirement which is smaller than that of the first voltage limiting module.
7 . The integrated circuit according to claim 5 , wherein the first voltage limiting module includes N1 first transistors in parallel, N1 being greater than 1 and said at least one second voltage limiting module includes N2 second transistors in parallel, N1 being greater than N2.
8 . The integrated circuit according to claim 1 , wherein said domain includes a non-volatile memory circuit.
9 . A method, comprising:
in the presence of a positive electrostatic discharge on one of first signal input and/or output pads coupled to a domain of an integrated circuit, limiting voltage on the first signal input and/or output pad by circulating the current resulting from the positive electrostatic discharge through a first voltage limiting module;
in the presence of a positive electrostatic discharge on a second pad configured to receive, during operation of the integrated circuit, a first power supply voltage, limiting voltage on an input terminal of at least one second voltage limiting module by distributing current resulting from the positive electrostatic discharge into:
a first current circulating in the first voltage limiting module and in a blocking diode coupled between the second pad, the first signal input and/or output pad and the input of the first voltage limiting module; and
at least one second current circulating in said at least one second voltage limiting module, said at least one second current being lower than the first current; and
during the operation of the integrated circuit, outputting, to said domain, at least one second power supply voltage equal to the voltage present at said input terminal of said at least one second voltage limiting module.
10 . The method according to claim 9 , wherein said at least one second current also circulates in a resistive element coupled between said input terminal of the corresponding second current limiting module and the second pad.
11 . An integrated circuit providing protection against electrostatic discharge, comprising:
a power supply voltage pad;
a ground reference pad;
a signal pad;
a first diode having an anode coupled to the signal pad and a cathode coupled to a first intermediate node;
a second diode have an anode coupled to the power supply voltage pad and a cathode coupled to the first intermediate node;
a first voltage limiting circuit having a first terminal coupled to the first intermediate node and a second terminal coupled to the ground reference pad, said first voltage limiting circuit configured to conduct a first current from the first terminal to the second terminal in response to a positive electrostatic discharge at the signal pad;
a resistance coupled between the power supply voltage pad and a second intermediate node;
a second voltage limiting circuit having a third terminal coupled to the second intermediate node and a fourth terminal coupled to the ground reference pad, said second voltage limiting circuit configured to conduct a second current less than the first current from the third terminal to the fourth terminal in response to a positive electrostatic discharge at the power supply voltage pad; and
wherein a power supply voltage for a circuit domain is output at the second intermediate node.
12 . The circuit of claim 11 , wherein said first voltage limiting circuit comprises a first lateral bipolar transistor having a collector connected to first terminal, an emitter connected to the second terminal and a base connected to the second terminal by a first base resistor.
13 . The circuit of claim 11 , wherein said second voltage limiting circuit comprises a second lateral bipolar transistor having a collector connected to the third terminal, an emitter connected to the fourth terminal and a base connected to the fourth terminal by a second base resistor.