Planarization method
A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.
1 . A planarization method, comprising:
depositing a silicon layer on a substrate, wherein a top surface of the silicon layer comprises:
a lower portion; and
a bump portion protruding upwards from the lower portion;
performing an ion bombardment etching process to the silicon layer for reducing a surface step height of the silicon layer, wherein the top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process; and
performing a chemical mechanical polishing process to the post-etching top surface of the silicon layer.
2 . The planarization method according to claim 1 , wherein the distance between the topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process is greater than or equal to 200 angstroms and less than or equal to 600 angstroms.
3 . The planarization method according to claim 1 , wherein the distance between the topmost portion of the post-etching top surface and the bottommost portion of the post-etching top surface in the vertical direction is greater than or equal to 10 angstroms and less than or equal to 60 angstroms.
4 . The planarization method according to claim 1 , wherein a gas used in the ion bombardment etching process comprises germanium.
5 . The planarization method according to claim 1 , wherein the silicon layer is an amorphous silicon layer.
6 . The planarization method according to claim 1 , wherein the post-etching top surface of the silicon layer is an uneven surface.
7 . The planarization method according to claim 1 , wherein a part of the silicon layer is removed by the chemical mechanical polishing process, and the post-etching top surface is planarized by the chemical mechanical polishing process.
8 . The planarization method according to claim 1 , wherein the substrate comprises:
a base layer; and
fin-shaped structures, wherein each of the fin-shaped structures protrudes upwards from a top surface of the base layer, and the bump portion is located above the fin-shaped structures in the vertical direction.
9 . The planarization method according to claim 8 , further comprising;
forming an isolation structure on the substrate before the silicon layer is formed, wherein a top surface of the isolation structure is lower than a top surface of each of the fin-shaped structures in the vertical direction, the silicon layer is formed straddling the fin-shaped structures, and the silicon layer contacts the top surface of the isolation structure.
10 . The planarization method according to claim 9 , further comprising;
forming a dielectric layer on each of the fin-shaped structures after the isolation structure is formed and before the silicon layer is formed, wherein each of the fin-shaped structures is a semiconductor fin-shaped structure, and the silicon layer is a gate material layer.
11 . The planarization method according to claim 1 , wherein the ion bombardment etching process is performed in an ion implantation apparatus.
12 . The planarization method according to claim 11 , wherein an ion implantation energy of the ion bombardment etching process ranges from 10 keV to 30 keV.
13 . The planarization method according to claim 11 , wherein an ion implantation dose of the ion bombardment etching process ranges from 10 14 ions/cm 2 to 10 16 ions/cm 2 .
14 . The planarization method according to claim 11 , wherein the ion bombardment etching process comprises a germanium ion bombardment process.