BEOL INTEGRATION SOLUTION BASED ON DIRECT CMP TO IMPROVE INTERMETAL DIELECTRIC LAYER
A process that helps ensure uniform height of conductive structures formed among intermetal dielectric layers of a wafer. When a metal layer is deposited on a first intermetal dielectric layer, a sealing layer is formed on the metal layer either before or after the metal layer is patterned to form metal interconnect structures. A first interlevel dielectric sub-layer is then formed on the sealing layer. A chemical mechanical planarization (CMP) process is then performed on the first interlevel dielectric sub-layer using the sealing layer as an etch stop. A second interlevel dielectric sub-layer is then formed on the first interlevel dielectric sub-layer.
1 . A method, comprising:
forming a transistor;
forming a first intermetal dielectric layer above the transistor;
forming a plurality of metal lines with a sealing layer covering at least a top of each metal line;
forming a first intermetal dielectric sub-layer between the metal lines and on the sealing layer above the metal lines; and
performing a CMP process on the first intermetal dielectric sub-layer including using the sealing layer as an etch stop layer to stop the CMP process.
2 . The method of claim 1 , wherein forming the metal lines and the sealing layer includes:
forming a metal stack on the first intermetal dielectric layer;
patterning the metal stack to form the metal lines on the first intermetal dielectric layer; and
forming the sealing layer on the tops and sidewalls of the metal lines and on the exposed surface of the first intermetal dielectric layer between the metal lines.
3 . The method of claim 1 , wherein forming the metal lines and the sealing layer includes:
forming a metal stack on the first intermetal dielectric layer;
forming the sealing layer on a top of the metal stack; and
patterning the sealing layer and the metal stack to form the plurality of metal lines with the sealing layer on the top of the metal lines.
4 . The method of claim 1 , wherein performing the CMP process includes:
performing a first CMP step corresponding to a timed CMP step; and
performing a second CMP step after the time CMP step including using the sealing layer as the etch stop,
and wherein the first CMP step includes using a first slurry, wherein the second CMP step includes using a second slurry different from the first etch chemistry.
5 . The method of claim 1 , wherein the first intermetal dielectric layer is silicon oxide.
6 . The method of claim 1 , comprising depositing a second intermetal dielectric sub-layer on the first intermetal dielectric sub-layer.
7 . The method of claim 6 , wherein the second intermetal dielectric sub-layer has a top surface that is substantially planar without CMP.
8 . The method of claim 6 , wherein the first intermetal dielectric sub-layer and the second intermetal dielectric sub-layer collectively form a second intermetal dielectric layer.
9 . The method of claim 6 , comprising:
exposing a top surface of one of the metal lines by forming a trench in the second intermetal dielectric sub-layer; and
forming a conductive via in the trench in contact with the top surface of the metal line.
10 . The method of claim 6 , wherein a first distance between a top surface of a first one of the metal lines and a top surface of the second intermetal dielectric sub-layer is substantially the same as a distance between a top surface of a second one of the metal lines and the top surface of the second intermetal dielectric sub-layer center, wherein the first one of the metal lines is in an integrated circuit near a center of a wafer, wherein the second one of the metal lines in a second integrated circuit near an edge of the wafer.
11 . The method of claim 1 , wherein the sealing layer is made of one of: silicon nitride, silicon carbonitride (SiCN), aluminum nitride (AlN), alumina (Al 2 O 3 ), hafnium oxide (HfO 2 ), Hafnium alumino-oxide (Hf x Al y O z ).
12 . The method of claim 1 , wherein the sealing layer has a thickness greater than or equal to 50 nm and less than or equal to 500 nm.
13 . An integrated circuit, comprising:
a transistor;
a first intermetal dielectric layer above the transistor;
a plurality of metal lines on the first intermetal dielectric layer;
a sealing layer at least on top of the metal lines;
a second intermetal dielectric layer on the first intermetal dielectric layer and on the sealing layer.
14 . The integrated circuit of claim 13 , wherein the second intermetal dielectric layer includes:
a first intermetal dielectric sub-layer having a top surface substantially coplanar with a top surface of the sealing layer; and
a second intermetal dielectric sub-layer on the first intermetal dielectric sub-layer, and wherein a top surface of the second intermetal dielectric layer is substantially equidistant from a top of each of the metal lines.
15 . The integrated circuit of claim 14 , wherein the first and second intermetal dielectric sub-layers are of a same material.
16 . The integrated circuit of claim 13 , wherein the transistor is a GaN transistor.
17 . The integrated circuit of claim 13 , wherein:
the sealing layer continuously covers also sidewalls of the metal lines and a top surface of the first intermetal dielectric layer between the metal lines; and
the second intermetal dielectric layer is on the sealing layer between the metal lines.
18 . An integrated circuit, comprising:
a first intermetal dielectric layer;
a first metal line on the first intermetal dielectric layer;
a second metal line on the first intermetal dielectric layer;
a sealing layer continuously covering top surfaces and sidewalls of the first and second metal lines and a top surface of the first intermetal dielectric layer between the first and second metal lines; and
a second intermetal dielectric layer on the sealing layer above and between the first and second metal lines.
19 . The integrated circuit of claim 18 , wherein the sealing layer has a thickness greater than or equal to 50 nm and less than or equal to 500 nm.
20 . The integrated circuit of claim 18 , comprising a plurality of transistors below the first intermetal dielectric layer.