SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A semiconductor device includes a substrate with first conductivity type and an epitaxial layer; a first trench and a second trench in the epitaxial layer, the depth of the first trench being greater than that of the second trench; a first gate structure including a first gate in the first trench and a first gate dielectric layer; a second gate structure including a second gate in the second trench and a second gate dielectric layer between the second gate and the epitaxial layer; a body region with second conductivity type being spaced apart from the first gate dielectric layer and being contiguous with the second gate dielectric layer; a first electrode region having first conductivity type; a third gate structure on the epitaxial layer and partially overlapping with the body region; and a second electrode. The Avalanche Energy, Single Pulse (EAS) durability of the semiconductor device is improved.
1 . A semiconductor device, comprising:
a substrate ( 110 ) having a first conductivity type;
an epitaxial layer ( 120 ) having the first conductivity type located on the substrate ( 110 );
a first trench (T 1 ) and a second trench (T 2 ) located in the epitaxial layer ( 120 ), wherein in the direction from the epitaxial layer ( 120 ) to the substrate ( 110 ), a depth of the first trench (T 1 ) in the epitaxial layer ( 120 ) is greater than a depth of the second trench (T 2 ) in the epitaxial layer ( 120 );
a first gate structure ( 130 ) including a first gate (TG 1 ) at least partially located in the first trench (T 1 ), and a first gate dielectric layer ( 131 ) between the first gate (TG 1 ) and the epitaxial layer ( 120 );
a second gate structure ( 140 ) including a second gate (TG 2 ) at least partially located in the second trench (T 2 ), and a second gate dielectric layer ( 141 ) between the second gate (TG 2 ) and the epitaxial layer ( 120 );
a first body region ( 150 A) with a second conductivity type located in the epitaxial layer ( 120 ) between the first gate structure ( 130 ) and the second gate structure ( 140 ), the first body region ( 150 A) being spaced apart from the first gate dielectric layer ( 131 ) and being contiguous with the second gate dielectric layer ( 141 ), wherein the second conductivity type is different from the second conductivity type;
a first electrode region ( 160 ) having the first conductivity type located in the first body region ( 150 A);
a third gate structure (PG′) located on a top surface of the epitaxial layer ( 120 ), wherein the third gate structure (PG′) partially overlaps the first body region ( 150 A); and
a second electrode ( 170 ) located under the substrate ( 110 ).
2 . The semiconductor device according to claim 1 , wherein an extending direction of the first trench (T 1 ) and the second trench (T 2 ) is the first direction (Y), and a size of the first trench (T 1 ) in the second direction (X) is larger than a size of the second trench (T 2 ) in the second direction (X), wherein the second direction (X) is substantially perpendicular to the first direction (Y).
3 . The semiconductor device according to claim 1 , wherein the third gate structure (PG′) partially overlaps the first gate dielectric layer ( 131 ), and the third gate structure (PG′) does not overlap the first gate (TG 1 ).
4 . The semiconductor device according to claim 1 , further comprising:
a first doped region ( 180 A) with the second conductivity type located in the epitaxial layer ( 120 ) and contiguous with the first gate dielectric layer ( 131 ), wherein the first doped region ( 180 A) is separated from the first body region ( 150 A) by the epitaxial layer ( 120 ).
5 . The semiconductor device of claim 1 , wherein the first gate dielectric layer ( 131 ) comprises a first portion ( 1311 ) on a first sidewall of the first trench (T 1 ), a second portion ( 1312 ) on a second sidewall of the first trench (T 1 ) and a third portion ( 1313 ) at a bottom of the first trench (T 1 ), wherein the third portion ( 1313 ) connects the first portion ( 1311 ) with the second portion ( 1312 );
wherein the semiconductor device further comprises:
a second body region ( 150 B), wherein the first body region ( 150 A) and the second body region ( 150 B) are respectively located on opposite sides of the first gate structure ( 130 );
a fourth gate structure (PG 1 ′) located on the top surface of the epitaxial layer ( 120 );
wherein the third gate structure (PG′) partially overlaps the first portion ( 1311 ) and partially overlaps the first body region ( 150 A);
wherein the fourth gate structure (PG 1 ′) partially overlaps the second portion ( 1312 ) and partially overlaps the second body region ( 150 B).
6 . The semiconductor device according to claim 5 , wherein the semiconductor device further comprises a first doped region ( 180 A) and a second doped region ( 180 B), wherein the first doped region ( 180 A) and the second doped region ( 180 B) are located on opposite sides of the first gate structure ( 130 ) respectively;
wherein the first doped region ( 180 A) and the first body region ( 150 A) are separated by the epitaxial layer ( 120 ) and is contiguous with the first portion ( 1311 ); and
wherein the second doped region ( 180 B) and the second body region ( 150 B) are separated by the epitaxial layer ( 120 ) and the second doped region ( 180 B) is contiguous with the second portion ( 1312 ).
7 . The semiconductor device according to claim 1 , further comprising:
a first spacer (SP 1 ) and a second spacer (SP 2 ) located on opposite sides of the third gate structure (PG′), wherein the first spacer (SP 1 ) is located on a surface of the first gate dielectric layer ( 131 ), the second spacer (SP 2 ) is located on a surface of the first body region ( 150 A).
8 . A semiconductor device, comprising:
a substrate ( 110 ) having a first conductivity type;
an epitaxial layer ( 120 ) having the first conductivity type located on the substrate ( 110 );
a first trench (T 1 ) and a second trench (T 2 ) located in the epitaxial layer ( 120 );
a first gate structure ( 130 ) including a first gate (TG 1 ) at least partially located in the first trench (T 1 ), and a first gate dielectric layer ( 131 ) between the first gate (TG 1 ) and the epitaxial layer ( 120 );
a second gate structure ( 140 ) including a second gate (TG 2 ) at least partially located in the second trench (T 2 ), and a second gate dielectric layer ( 141 ) located between the second gate (TG 2 ) and the epitaxial layer ( 120 ), wherein a depth of the first gate (TG 1 ) in the epitaxial layer ( 120 ) is greater than a depth of the second gate (TG 2 ) in the epitaxial layer ( 120 );
a first body region ( 150 A) with the second conductivity type located in the epitaxial layer ( 120 ) between the first gate structure ( 130 ) and the second gate structure ( 140 ), the first body region ( 150 A) being spaced apart from the first gate dielectric layer ( 131 ) and being contiguous with the second gate dielectric layer ( 141 ), and the second conductivity type is different from the second conductivity type;
a first electrode region ( 160 ) having the first conductivity type located in the first body region ( 150 A);
a third gate structure (PG′) located on a top surface of the epitaxial layer ( 120 ), wherein the third gate structure (PG′) partially overlaps the first body region ( 150 A); and
a second electrode ( 170 ) located under the substrate ( 110 ).
9 . The semiconductor device according to claim 8 , wherein an extending direction of the first gate (TG 1 ) and the second gate (TG 2 ) is the first direction (Y), and a size of the first gate (TG 1 ) in the second direction (X) is larger than a size of the second gate (TG 2 ) in the second direction, wherein the second direction (X) is substantially perpendicular to the first direction (Y).
10 . The semiconductor device according to claim 8 , wherein the third gate structure (PG′) partially overlaps the first gate dielectric layer ( 131 ), and the third gate structure (PG′) does not overlap the first gate (TG 1 ).
11 . The semiconductor device according to claim 8 , further comprising:
a first doped region ( 180 A) with the second conductivity type located in the epitaxial layer ( 120 ) and contiguous with the first gate dielectric layer ( 131 ), wherein the first doped region ( 180 A) is separated from the first body region ( 150 A) by the epitaxial layer ( 120 ).
12 . The semiconductor device of claim 8 , wherein the first gate dielectric layer ( 131 ) comprises a first portion ( 1311 ) on a first sidewall of the first trench (T 1 ), a second portion ( 1312 ) on a second sidewall of the first trench (T 1 ) and a third portion ( 1313 ) at a bottom of the first trench (T 1 ), wherein the third portion ( 1313 ) connects the first portion ( 1311 ) with the second portion ( 1312 );
wherein the semiconductor device further comprises:
a second body region ( 150 B), wherein the first body region ( 150 A) and the second body region ( 150 B) are respectively located on opposite sides of the first gate structure ( 130 ); and
a fourth gate structure (PG 1 ′) located on the top surface of the epitaxial layer ( 120 );
wherein the third gate structure (PG′) partially overlaps the first portion ( 1311 ) and partially overlaps the first body region ( 150 A);
wherein the fourth gate structure (PG 1 ′) partially overlaps the second portion ( 1312 ) and partially overlaps the second body region ( 150 B).
13 . A method of manufacturing a semiconductor device, comprising:
providing a substrate ( 110 ) having a first conductivity type;
forming an epitaxial layer ( 120 ) with the first conductivity type on the substrate ( 110 );
forming a first trench (T 1 ) and a second trench (T 2 ) in the epitaxial layer ( 120 ), wherein a depth of the first trench (T 1 ) in the epitaxial layer ( 120 ) is greater than a depth of the second trench (T 2 ) in the epitaxial layer ( 120 );
forming a first gate structure ( 130 ) in the first trench (T 1 ), and a second gate structure ( 140 ) in the second trench (T 2 ), wherein the first gate structure ( 130 ) comprises a first gate (TG 1 ) at least partially located in the first trench (T 1 ), and a gate dielectric layer ( 131 ) located between the first gate (TG 1 ) and the epitaxial layer ( 120 ), the second gate structure ( 140 ) comprises a second gate (TG 2 ) at least partially located in the second trench (T 2 ), and a second gate dielectric layer ( 141 ) located between the second gate (TG 2 ) and the epitaxial layer ( 120 );
forming a third gate structure (PG′) on a top surface of the epitaxial layer ( 120 );
after forming the third gate structure (PG′), a doping process is performed to form a first body region ( 150 A) having a second conductivity type in the epitaxial layer ( 120 ) between the first gate structure ( 130 ) and the second gate structure ( 140 ), wherein the first body region ( 150 A) partially overlaps the third gate structure (PG′), wherein the first body region ( 150 A) is spaced apart from the first gate dielectric layer ( 131 ) and is contiguous with the second gate dielectric layer ( 141 ), and wherein the second conductivity type is different from the first conductivity type;
forming a first electrode region ( 160 ) having the first conductivity type in the first body region ( 150 A); and
forming a second electrode ( 170 ) under the substrate ( 110 ).
14 . The method of claim 13 , wherein a bottom of the first trench (T 1 ) is closer to the substrate ( 110 ) than a bottom of the second trench (T 2 );
wherein an extending direction of the first trench (T 1 ) and the second trench (T 2 ) is the first direction (Y), and a size of the first trench (T 1 ) in the second direction (X) is larger than a size of the second trench (T 2 ) in the second direction (X), and the second direction (X) is substantially perpendicular to the first direction (Y).
15 . The method of claim 13 , wherein said forming a first gate structure ( 130 ) in the first trench (T 1 ), and a second gate structure ( 140 ) in the second trench (T 2 ) comprises:
forming a dielectric material layer (D) on a bottom and sidewalls of the first trench (T 1 ), a bottom and sidewalls of the second trench (T 2 ), and the top surface of the epitaxial layer ( 120 );
after forming the dielectric material layer (D), filling conductive material into the first trench (T 1 ) and the second trench (T 2 ) to form the first gate (TG 1 ) and the second gate (TG 2 ); and
removing portion of the dielectric material layer (D) on the top surface of the epitaxial layer ( 120 ), wherein the dielectric material layer (D) on the bottom and sidewalls of the first trench (T 1 ) serves as the first gate dielectric layer ( 131 ) and the dielectric material layer (D) on the bottom and sidewalls of the second trench (T 2 ) serves as the second gate dielectric layer ( 141 ).
16 . The method of claim 13 , wherein before forming the first body region ( 150 A), doping at least one of the first gate (TG 1 ) and the second gate (TG 2 );
wherein the method further comprises:
after forming the first body region ( 150 A), performing a first annealing.
17 . The method of claim 16 , wherein said forming the third gate structure (PG′) comprises:
forming a third gate dielectric layer (GOX) on the top surface of the epitaxial layer ( 120 );
after forming the third gate dielectric layer (GOX), performing a second annealing; and
forming a third gate (PG) on the third gate dielectric layer (GOX);
wherein, before forming the third gate dielectric layer (GOX), at least one of the first gate (TG 1 ) and the second gate (TG 2 ) is doped.
18 . The method of claim 13 , wherein the third gate structure (PG′) partially overlaps the first gate dielectric layer ( 131 ), and the third gate structure (PG′) does not overlap the first gate (TG 1 ).
19 . The method of claim 18 , wherein:
the doping process further forming a first doped region ( 180 A) in the epitaxial layer ( 120 ), wherein the first doped region ( 180 A) is contiguous with the first gate dielectric layer ( 131 ), wherein the first doped region ( 180 A) and the first body region ( 150 A) are separated by the epitaxial layer ( 120 ).
20 . The method of claim 18 , further comprising:
forming a first spacer (SP 1 ) and a second spacer (SP 2 ) on opposite sides of the third gate structure (PG′), wherein the first spacer (SP 1 ) is located on a surface of the first gate dielectric layer ( 131 ), the second spacer (SP 2 ) is located on a surface of the first body region ( 150 A).
21 . The method of claim 20 , further comprising:
after forming the first spacer (SP 1 ) and the second spacer (SP 2 ), forming a first silicide layer (SA 1 ), a second silicide layer (SA 2 ), a third silicide layer (SA 3 ) and a fourth silicide layer (SA 4 );
wherein, the first silicide layer (SA 1 ) is located on a top surface of the first gate electrode (TG 1 ), and the second silicide layer (SA 2 ) is located on a top surface of the second gate electrode (TG 2 ), the third silicide layer (SA 3 ) is located on a top surface of the third gate structure (PG′), and the fourth silicide layer (SA 4 ) is located on a top surface of the first electrode region ( 160 ).