Semiconductor device and fabrication method thereof
A semiconductor device includes a substrate of first conductive type and an epitaxial layer; a first trench in the epitaxial layer; a first gate electrode structure in the first trench; a body region and the doped region of second conductivity type in the epitaxial layer, the body region is spaced apart from the first gate dielectric layer of the first gate electrode structure, the doped region is separated from the body region by the epitaxial layer and is contiguous with the first gate dielectric layer; a first electrode region of first conductivity type in the body region; a third gate structure on a top surface of the epitaxial layer, including a third gate and a third gate dielectric layer, the third gate structure partially overlaps the first gate dielectric layer and partially overlaps the body region; and a second electrode.
1 . A semiconductor device, comprising:
a substrate having a first conductivity type;
an epitaxial layer having the first conductivity type on the substrate;
a first trench in the epitaxial layer;
a first gate structure including a first gate in the first trench, and a first gate dielectric layer between the first gate and the epitaxial layer, wherein the first gate dielectric layer includes a first portion and a second portion on two opposite sides of the first gate structure, respectively;
a first body region and a second body region having a second conductivity type in the epitaxial layer and on the two opposite sides of the first gate structure, respectively, wherein the first body region and the second body region are spaced from the first gate dielectric layer, wherein the second conductivity type is different from the first conductivity type;
a first doped region and a second doped region having the second conductivity type and being disposed on the two opposite sides of the first gate structure, respectively,
wherein the first doped region is separated from the first body region by the epitaxial layer and is contiguous with the first portion of the first gate dielectric layer;
wherein the second doped region is separated from the second body region by the epitaxial layer and is contiguous with the second portion of the first gate dielectric layer;
a third gate structure and a fourth gate structure on a top surface of the epitaxial layer and on the two opposite sides of the first gate structure, respectively, wherein the third gate structure partially overlaps the first portion of the first gate dielectric layer and partially overlaps the first body region and the fourth gate structure partially overlaps the second portion of the first gate dielectric layer and partially overlaps the second body region; and
a second electrode under the substrate.
2 . The semiconductor device according to claim 1 , wherein the third gate structure does not overlap with the first gate.
3 . The semiconductor device according to in claim 1 , further comprising:
a first spacer and a second spacer located on opposite sides of the third gate structure, wherein the first spacer is located on a surface of the first gate dielectric layer, and the second spacer is located on a surface of the first body region.
4 . The semiconductor device according to claim 1 , wherein an extending direction of the third gate structure is first direction, and a size of an overlapping portion between the third gate structure and the first gate dielectric layer in second direction is less than or equal to 0.1 micrometers, and the second direction is substantially perpendicular to the first direction.
5 . The semiconductor device according to claim 1 , wherein the first gate dielectric layer includes a third portion on a bottom of the first trench, wherein the third portion connects the first portion with the second portion.
6 . The semiconductor device according to claim 1 , wherein:
the first conductivity type is N type and the second conductivity type is P type;
wherein a first electrode region having the first conductivity type is disposed in the first body region, and wherein the first electrode region is a source region, and the second electrode is a drain.
7 . A method for manufacturing a semiconductor device, comprising:
providing a substrate having a first conductivity type;
forming an epitaxial layer having the first conductivity type on the substrate;
forming a first trench in the epitaxial layer;
forming a first gate structure in the first trench, wherein the first gate structure comprises a first gate in the first trench, and a first gate dielectric layer between the first gate and the epitaxial layer;
forming a third gate structure on a top surface of the epitaxial layer, wherein the third gate structure comprises a third gate and a third gate dielectric layer between the epitaxial layer and the third gate, wherein the third gate structure partial overlap the first gate dielectric layer;
after forming the third gate structure, performing a doping process to form a first body region and a first doped region having a second conductivity type in the epitaxial layer, wherein the first body region partially overlaps the third gate structure, wherein the first body region is spaced apart from the first gate dielectric layer, and the first doped region is contiguous with the first gate dielectric layer, wherein the first doped region is separated from the first body region by the epitaxial layer, and wherein the second conductivity type is different from the first conductivity type;
forming a first electrode region having the first conductivity type in the first body region; and
forming a second electrode under the substrate.
8 . The method of claim 7 , further comprising:
forming a first spacer and a second spacer on opposite sides of the third gate structure, wherein the first spacer is located on a surface of the first gate dielectric layer, the second spacer is located on a surface of the first body region.
9 . The method of claim 8 , further comprising:
after forming the first spacer and the second spacer, forming a first silicide layer, a third silicide layer and a fourth silicide layer;
wherein the first silicide layer is located on a top surface of the first gate, and the third silicide layer is located on a top surface of the third gate structure, and the fourth silicide layer is located on a top surface of the first electrode region.
10 . The method of claim 7 , wherein an extending direction of the third gate structure is first direction, and a size of an overlapping portion between the third gate structure and the first gate dielectric layer in the second direction is less than or equal to 0.1 micrometers, and wherein the second direction is substantially perpendicular to the first direction.
11 . The method of claim 7 , further comprising:
doping the first gate.
12 . The method of claim 11 , wherein the first gate is doped before forming the first body region;
wherein the method further comprises:
performing a first annealing after forming the first body region.
13 . The method of claim 12 , wherein said forming the third gate structure comprises:
forming the third gate dielectric layer on the top surface of the epitaxial layer;
after forming the third gate dielectric layer, performing a second annealing; and
forming the third gate on the third gate dielectric layer;
wherein before forming the third gate dielectric layer, the first gate is doped.
14 . The method of claim 7 , further comprising:
when forming the third gate structure, simultaneously forming a fourth gate structure on a top surface of the epitaxial layer, and the third gate structure and the fourth gate structure are respectively located on opposite sides of the first gate structure, wherein the fourth gate structure comprises a fourth gate and a fourth gate dielectric layer between the epitaxial layer and the fourth gate, wherein the fourth gate structure partial overlaps the first gate dielectric layer.
15 . The method of claim 7 , further comprising:
when performing the doping process to form the first body region and the first doped region, simultaneously forming a second doped region having the second conductivity type in the epitaxial layer, and the first doped region and the second doped region are respectively located on opposite sides of the first gate structure, and the second doped region is contiguous with the first gate dielectric layer.