Sharable usage-based disturbance circuitry
Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.
1 . An apparatus comprising:
a memory device comprising:
at least two banks comprising memory cells arranged in columns along a direction of a first vertical axis and arranged in rows along a direction of a second horizontal axis that is substantially perpendicular to the first vertical axis, each bank of the at least two banks comprising multiple sections of the memory cells, the multiple sections positioned along the direction of the first vertical axis, the multiple sections comprising two sections positioned proximate to each other along the first vertical axis, the two sections having a total length defined relative to the first vertical axis, each section of the two sections comprising multiple subarrays of the memory cells positioned along the direction of the second horizontal axis; and
multiple circuits positioned along the direction of the first vertical axis, each circuit of the multiple circuits comprising at least one of the following: a counter circuit or an error-correction-code circuit, the multiple circuits comprising a circuit coupled to two sections of a first bank of the at least two banks and coupled to two sections of a second bank of the at least two banks, the circuit positioned between the first bank and the second bank along the direction of the second horizontal axis, the circuit having a length defined relative to the first vertical axis, the length being less than or equal to the total length, the circuit and groupings of the two sections of the at least two banks being positioned along the direction of the second horizontal axis such that the length of the circuit overlaps at least a portion of the total length of the two sections along the first vertical axis.
2 . The apparatus of claim 1 , wherein:
the two sections of each of the at least two banks comprise a first section and a second section;
each subarray of the multiple subarrays has a length defined relative to the first vertical axis; and
the length of the circuit is greater than a summation of the lengths of a subarray of the first and second sections.
3 . The apparatus of claim 2 , wherein:
each bank of the at least two banks comprises multiple sense amplifiers positioned between a subarray of each section of the two sections; and
the multiple sense amplifiers are coupled to the subarray of each section of the two sections and are coupled to the circuit.
4 . The apparatus of claim 2 , wherein each subarray of the multiple subarrays comprises at least one row of the memory cells that are positioned along the direction of the second horizontal axis.
5 . The apparatus of claim 1 , wherein the circuit is positioned adjacent to the two sections of the at least two banks in the direction of the second horizontal axis.
6 . The apparatus of claim 1 , wherein the circuit is configured to detect conditions associated with usage-based disturbance within the two sections of the at least two banks.
7 . The apparatus of claim 6 , wherein:
the two sections of the at least two banks are configured to store bits associated with detecting the usage-based disturbance; and
the circuit is configured to:
read the bits from a first section of the two sections of one of the at least two banks during a first time interval; and
read the bits from a second section of the two sections of the one of the at least two banks during a second time interval.
8 . The apparatus of claim 1 , wherein each circuit of the multiple circuits comprises a counter circuit and an error-correction-code circuit.
9 . The apparatus of claim 1 , wherein:
the multiple sections of each of the at least two banks comprise a first quantity of sections; and
the multiple circuits comprise a second quantity of circuits that is less than the first quantity of sections.
10 . The apparatus of claim 9 ,
wherein the second quantity of circuits is equal to approximately half the first quantity of sections.
11 . The apparatus of claim 1 , wherein the apparatus comprises a Compute Express Link® (CXL®) device.
12 . A method of manufacturing a die of a memory device, the method comprising:
disposing, on the die, a first bank and a second bank, each bank of the first and second banks comprising memory cells arranged in columns along a direction of a first vertical axis and arranged in rows along a direction of a second horizontal axis that is substantially perpendicular to the first vertical axis, each bank of the first and second banks comprising two sections of the memory cells, the two sections positioned along a first vertical axis, the two sections having a total length defined relative to the first vertical axis, each section of the two sections comprising multiple subarrays of the memory cells positioned along the direction of the second horizontal axis; and
disposing, on the die, a circuit having a length defined relative to the first vertical axis, the length being less than or equal to the total length, the circuit coupled to two sections of the first bank and two sections of the second bank, the circuit positioned between the first bank and the second bank along the direction of the second horizontal axis, the circuit and groupings of the two sections of the at least two banks being positioned along the direction of the second horizontal axis such that the length of the circuit overlaps at least a portion of the total length of the two sections along the first vertical axis.
13 . The method of claim 12 , wherein each subarray of the multiple subarrays comprises at least one row of memory cells that are positioned along the direction of the second horizontal axis.
14 . The method of claim 12 , wherein:
the two sections of each of the at least two banks comprise a first section and a second section;
each subarray of the multiple subarrays has a length defined relative to the first vertical axis; and
the length of the circuit is greater than a summation of the lengths of a subarray of the first and second sections.
15 . The method of claim 12 , wherein:
the two sections comprise a first section and a second section;
each section of the two sections comprises sense amplifiers; and
the method further comprises:
coupling the circuit to at least a portion of the sense amplifiers of the first section; and
coupling the circuit to at least a portion of the sense amplifiers of the second section.
16 . An apparatus comprising:
a memory device comprising:
at least two banks, each bank of the at least two banks comprising memory cells arranged in columns along a direction of a first vertical axis and arranged in rows along a direction of a second horizontal axis that is substantially perpendicular to the first vertical axis, each bank of the at least two banks comprising multiple sections of the memory cells positioned along the direction of the first vertical axis, each section of the multiple sections configured to store bits associated with mitigating usage-based disturbance, the multiple sections comprising a first quantity of sections, each section of the multiple sections comprising multiple subarrays positioned along the direction of the second horizontal axis; and
multiple circuits positioned along the direction of the first vertical axis, each circuit of the multiple circuits coupled to a corresponding adjacent pair of the multiple sections within each of the at least two banks, each circuit positioned between the at least two banks along the direction of the second horizontal axis, each circuit of the multiple circuits and groupings of the corresponding adjacent pairs of the multiple sections of the at least two banks positioned along the direction of the second axis such that a length of each circuit overlaps at least a portion of a total length of the corresponding adjacent pair of the multiple sections along the first vertical axis, each circuit of the multiple circuits coupled to the corresponding adjacent pair of the multiple sections and configured to read the bits associated with mitigating usage-based disturbance from the corresponding adjacent pair of the multiple sections, the multiple circuits comprising a second quantity of circuits that is less than the first quantity of sections.
17 . The apparatus of claim 16 , wherein the second quantity of circuits is equal to approximately half the first quantity of sections.
18 . The apparatus of claim 16 , wherein each circuit of the multiple circuits comprises at least one of the following:
a counter circuit; or
an error-correction-code circuit.
19 . The apparatus of claim 18 , wherein each circuit of the multiple circuits comprises at least one counter circuit and at least one error-correction-code circuit.
20 . The apparatus of claim 16 , wherein each circuit of the multiple circuits is configured to detect conditions associated with usage-based disturbance within the corresponding adjacent pair of the multiple sections within each of the at least two banks.