Systems for performing instructions to quickly convert and use tiles as 1D vectors
Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.
1 . A processor comprising:
a plurality of vector registers, each vector register of the plurality of vector registers to store a plurality of matrix data elements;
execution circuitry to execute an instruction to load a first plurality of source data elements from a first column and a second column of a first source tile to a first vector register of the plurality of vector registers, wherein a first subset of the first plurality of source data elements from the first column are to be interleaved with a second subset of the first plurality of source data elements from the second column within the first vector register, the first source tile comprising group of rows and columns of a first source matrix stored in a memory;
the execution circuitry further comprising:
a set of multipliers to perform a parallel multiplication of each data element of the first plurality of source data elements stored in the first vector register with a corresponding source data element of a second plurality of source data elements stored in a second vector register of the plurality of vector registers to generate a corresponding plurality of products, the second plurality of source data elements from a second source tile of a second source matrix to be multiplied with the first source matrix; and
accumulator circuitry to add groups of the corresponding plurality of products to corresponding accumulated data elements of an accumulation matrix to generate corresponding result data elements of a result matrix.
2 . The processor of claim 1 , wherein the accumulated data elements and result data elements have a width which is at least two times a width of the data elements of the first and second plurality of source data elements.
3 . The processor of claim 2 , wherein the accumulated data elements and result data elements comprise 32-bit floating-point data elements and the data elements of the first and second plurality of source data elements comprise 16-bit floating point data elements.
4 . The processor of claim 2 , wherein the accumulated data elements and result data elements comprise 32-bit integer data elements and the data elements of the first and second plurality of source data elements comprise 8-bit or 4-bit integer data elements.
5 . The processor of claim 1 , wherein source data elements from the first and second columns are interleaved in the first vector register in a sequential order in which source data elements from a same row are adjacent and in which at least one data element from a row is adjacent to another data element from a next sequential row when loaded in the first vector register.
6 . The processor of claim 1 , wherein the instruction includes a first operand to indicate an address of the first source tile in the memory and a second operand to indicate the first vector register.
7 . The processor of claim 1 , wherein the plurality of rows and columns of the first source matrix comprises 16 rows and 16 columns.
8 . A system comprising:
a memory; and
matrix operations circuitry coupled to the memory, the matrix operations circuitry comprising:
a plurality of vector registers, each vector register of the plurality of vector registers to store a plurality of matrix data elements;
execution circuitry to execute an instruction to load a first plurality of source data elements from a first column and a second column of a first source tile to a first vector register of the plurality of vector registers, wherein a first subset of the first plurality of source data elements from the first column are to be interleaved with a second subset of the first plurality of source data elements from the second column within the first vector register, the first source tile comprising group of rows and columns of a first source matrix stored in the memory;
the execution circuitry further comprising:
a set of multipliers to perform a parallel multiplication of each data element of the first plurality of source data elements stored in the first vector register with a corresponding source data element of a second plurality of source data elements stored in a second vector register of the plurality of vector registers to generate a corresponding plurality of products, the second plurality of source data elements from a second source tile of a second source matrix to be multiplied with the first source matrix; and
accumulator circuitry to add groups of the corresponding plurality of products to corresponding accumulated data elements of an accumulation matrix to generate corresponding result data elements of a result matrix.
9 . The system of claim 8 , wherein the accumulated data elements and result data elements have a width which is at least two times a width of the data elements of the first and second plurality of source data elements.
10 . The system of claim 9 , wherein the accumulated data elements and result data elements comprise 32-bit floating-point data elements and the data elements of the first and second plurality of source data elements comprise 16-bit floating point data elements.
11 . The system of claim 9 , wherein the accumulated data elements and result data elements comprise 32-bit integer data elements and the data elements of the first and second plurality of source data elements comprise 8-bit or 4-bit integer data elements.
12 . The system of claim 8 , wherein source data elements from the first and second columns are interleaved in the first vector register in a sequential order in which source data elements from a same row are adjacent and in which at least one data element from a row is adjacent to another data element from a next sequential row when loaded in the first vector register.
13 . The system of claim 8 , wherein the instruction includes a first operand to indicate an address of the first source tile in the memory and a second operand to indicate the first vector register.
14 . The system of claim 8 , wherein the plurality of rows and columns of the first source matrix comprises 16 rows and 16 columns.
15 . A system comprising:
a memory;
a processor; and
matrix operations circuitry coupled to the memory and the processor, the matrix operations circuitry comprising:
a plurality of vector registers, each vector register of the plurality of vector registers to store a plurality of matrix data elements;
execution circuitry to execute an instruction to load a first plurality of source data elements from a first column and a second column of a first source tile to a first vector register of the plurality of vector registers, wherein a first subset of the first plurality of source data elements from the first column are to be interleaved with a second subset of the first plurality of source data elements from the second column within the first vector register, the first source tile comprising group of rows and columns of a first source matrix stored in the memory;
the execution circuitry further comprising:
a set of multipliers to perform a parallel multiplication of each data element of the first plurality of source data elements stored in the first vector register with a corresponding source data element of a second plurality of source data elements stored in a second vector register of the plurality of vector registers to generate a corresponding plurality of products, the second plurality of source data elements from a second source tile of a second source matrix to be multiplied with the first source matrix; and
accumulator circuitry to add groups of the corresponding plurality of products to corresponding accumulated data elements of an accumulation matrix to generate corresponding result data elements of a result matrix.
16 . The system of claim 15 , wherein the accumulated data elements and result data elements have a width which is at least two times a width of the data elements of the first and second plurality of source data elements.
17 . The system of claim 16 , wherein the accumulated data elements and result data elements comprise 32-bit floating-point data elements and the data elements of the first and second plurality of source data elements comprise 16-bit floating point data elements.
18 . The system of claim 16 , wherein the accumulated data elements and result data elements comprise 32-bit integer data elements and the data elements of the first and second plurality of source data elements comprise 8-bit or 4-bit integer data elements.
19 . The system of claim 15 , wherein source data elements from the first and second columns are interleaved in the first vector register in a sequential order in which source data elements from a same row are adjacent and in which at least one data element from a row is adjacent to another data element from a next sequential row when loaded in the first vector register.
20 . The system of claim 15 , wherein the instruction includes a first operand to indicate an address of the first source tile in the memory and a second operand to indicate the first vector register.
21 . The system of claim 15 , wherein the plurality of rows and columns of the first source matrix comprises 16 rows and 16 columns.