Display panel, integrated chip, and display apparatus
Provided display panel includes pixel circuit and light emitting element. The pixel circuit includes a drive module including a drive transistor, and a bias adjustment module to provide a bias adjustment signal to a first pole or a second pole of the drive transistor. Operation modes of the display panel include a first mode and a second mode, and a brightness level of the display panel in the first mode is greater than a brightness level of the display panel in the second mode. An operation process of the pixel circuit includes a data writing frame and a holding frame; the data writing frame and the holding frame in the first mode respectively correspond to a bias adjustment signal of Vs11 and Vs12; the data writing frame and the holding frame in the second mode respectively correspond to a bias adjustment signal of Vs21 and Vs22; where |Vs11−Vs12|=|Vs21−Vs22|.
1. A display panel, comprising:
a pixel circuit and a light emitting element;
wherein the pixel circuit comprises a drive module, and a bias adjustment module;
wherein the drive module comprises a drive transistor; and
the bias adjustment module is configured to provide a bias adjustment signal to a first pole of the drive transistor or a second pole of the drive transistor;
wherein operation modes of the display panel comprise a first mode and a second mode, and a brightness level of the display panel in the first mode is greater than a brightness level of the display panel in the second mode; and
wherein an operation process of the pixel circuit comprises a data writing frame and a holding frame;
the data writing frame in the first mode corresponds to a bias adjustment signal of Vs11, and the holding frame in the first mode corresponds to a bias adjustment signal of Vs12;
the data writing frame in the second mode corresponds to a bias adjustment signal of Vs21, and the holding frame in the second mode corresponds to a bias adjustment signal of Vs22; and
|Vs11−Vs12|=|Vs21−Vs22|.
2. The display panel according to claim 1 , wherein one image frame of the display panel comprises a non-light-emitting stage and a light-emitting stage, and a duration of the light-emitting stage in the first mode is greater than a duration of the light-emitting stage in the second mode.
3. The display panel according to claim 1 , wherein
the pixel circuit further comprises a data writing module configured to provide a data signal to the drive transistor, and
wherein a data signal received by the drive transistor in the first mode is not equal to a data signal received by the drive transistor in the second mode.
4. The display panel according to claim 1 , wherein the pixel circuit further comprises a reset module and a compensation module, the reset module is configured to provide a reset signal to the drive transistor, and the compensation module is connected between a gate of the drive transistor and the second pole of the drive transistor; and
wherein the reset module is connected to the gate of the drive transistor, and the reset module is configured to provide a reset signal to the gate of the drive transistor in a reset stage; or, the reset module is connected to the first pole of the drive transistor or the second pole of the drive transistor, the reset module is also served as the bias adjustment module, and the reset module is configured to provide the bias adjustment signal to the first pole of the drive transistor or the second pole of the drive transistor in a bias adjustment stage.
5. The display panel according to claim 1 , wherein the pixel circuit further comprises an initialization module, and the initialization module is configured to provide an initialization signal to the light emitting element.
6. The display panel according to claim 5 , wherein
the data writing frame in the first mode corresponds to an initialization signal of Vi11, and the holding frame in the first mode corresponds to an initialization signal of Vi12; and
wherein |Vi11−Vi12|=|Vs21−Vs22|.
7. The display panel according to claim 5 , wherein
the data writing frame in the first mode corresponds to an initialization signal of Vi11, and the holding frame in the first mode corresponds to an initialization signal of Vi12; and
wherein |Vi11−Vi12|>|Vs21−Vs22|.
8. The display panel according to claim 5 , wherein
the data writing frame in the first mode corresponds to an initialization signal of Vi11, and the holding frame in the first mode corresponds to an initialization signal of Vi12; and
wherein |Vi11−Vi12|<Vs21−Vs22|.
9. An integrated chip, configured to provide the bias adjustment signal to the display panel according to claim 1 .
10. A display apparatus, comprising a display panel, wherein the display panel comprises:
a pixel circuit and a light emitting element;
wherein the pixel circuit comprises a drive module, and a bias adjustment module;
wherein the drive module comprises a drive transistor; and
the bias adjustment module is configured to provide a bias adjustment signal to a first pole of the drive transistor or a second pole of the drive transistor;
wherein operation modes of the display panel comprise a first mode and a second mode, and a brightness level of the display panel in the first mode is greater than a brightness level of the display panel in the second mode; and
wherein an operation process of the pixel circuit comprises a data writing frame and a holding frame;
the data writing frame in the first mode corresponds to a bias adjustment signal of Vs11, and the holding frame in the first mode corresponds to a bias adjustment signal of Vs12;
the data writing frame in the second mode corresponds to a bias adjustment signal of Vs21, and the holding frame in the second mode corresponds to a bias adjustment signal of Vs22; and
|Vs11−Vs12|=|Vs21−Vs22|.
11. A display panel, comprising:
a pixel circuit and a light emitting element;
wherein the pixel circuit comprises a drive module, a data writing module and a bias adjustment module;
the drive module comprises a drive transistor;
the data writing module is configured to provide a data signal to the drive transistor; and
the bias adjustment module is configured to provide a bias adjustment signal to a first pole of the drive transistor or a second pole of the drive transistor;
wherein operation modes of the display panel comprise a first mode and a second mode, and a brightness level of the display panel in the first mode is greater than a brightness level of the display panel in the second mode; and
wherein an operation process of the pixel circuit comprises a data writing frame and a holding frame;
the data writing frame in the first mode corresponds to a bias adjustment signal of Vs11, and the holding frame in the first mode corresponds to a bias adjustment signal of Vs12;
the data writing frame in the second mode corresponds to a bias adjustment signal of Vs21, and the holding frame in the second mode corresponds to a bias adjustment signal of Vs22; and
|Vs11−Vs12|=|Vs21−Vs22|.
12. The display panel according to claim 11 , wherein one image frame of the display panel comprises a non-light-emitting stage and a light-emitting stage, and a duration of the light-emitting stage in the first mode is greater than a duration of the light-emitting stage in the second mode.
13. The display panel according to claim 11 , wherein the pixel circuit further comprises a reset module and a compensation module, the reset module is configured to provide a reset signal to the drive transistor, and the compensation module is connected between a gate of the drive transistor and the second pole of the drive transistor; and
wherein the reset module is connected to the gate of the drive transistor, and the reset module is configured to provide a reset signal to the gate of the drive transistor in a reset stage; or, the reset module is connected to the first pole of the drive transistor or the second pole of the drive transistor, the reset module is also served as the bias adjustment module, and the reset module is configured to provide the bias adjustment signal to the first pole of the drive transistor or the second pole of the drive transistor in a bias adjustment stage.
14. The display panel according to claim 11 , wherein the pixel circuit further comprises an initialization module, and the initialization module is configured to provide an initialization signal to the light emitting element.
15. The display panel according to claim 14 , wherein
the data writing frame in the first mode corresponds to an initialization signal of Vi11, and the holding frame in the first mode corresponds to an initialization signal of Vi12; and
wherein |Vi11−Vi12|=|Vs21−Vs22|.
16. The display panel according to claim 14 , wherein
the data writing frame in the first mode corresponds to an initialization signal of Vi11, and the holding frame in the first mode corresponds to an initialization signal of Vi12; and
wherein |Vi11−Vi12|>|Vs21−Vs22|.
17. The display panel according to claim 14 , wherein
the data writing frame in the first mode corresponds to an initialization signal of Vi11, and the holding frame in the first mode corresponds to an initialization signal of Vi12; and
wherein |Vi11−Vi12|<|Vs21−Vs22|.
18. An integrated chip, configured to provide the bias adjustment signal to the display panel according to claim 11 .
19. A display apparatus, comprising the display panel according to claim 11 .